linux/arch/mips/mm
Ralf Baechle a76ab5c10d [MIPS] MT: Fix bug in multithreaded kernels.
When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().

As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.

This is where the following code in local_r4k_flush_cache_page() strikes:

        /*
         * If ownes no valid ASID yet, cannot possibly have gotten
         * this page into the cache.
         */
        if (cpu_context(smp_processor_id(), mm) == 0)
                return;

On VSMP and SMTC had a function of cpu_context() for each CPU(TC).

So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.

While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().

Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.

This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
..
c-r3k.c [MIPS] c-r3k: Implement flush_cache_range() 2007-10-29 19:35:36 +00:00
c-r4k.c [MIPS] MT: Fix bug in multithreaded kernels. 2007-10-29 19:35:37 +00:00
c-tx39.c [MIPS] Allow hardwiring of the CPU type to a single type for optimization. 2007-10-11 23:46:15 +01:00
cache.c Remove dma_cache_(wback|inv|wback_inv) functions 2007-10-17 08:42:57 -07:00
cerr-sb1.c [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
cex-gen.S
cex-sb1.S
dma-default.c [MIPS] Cleanup random difference between the lmo and kernel.org tree. 2007-10-29 19:35:33 +00:00
extable.c
fault.c pid namespaces: define is_global_init() and is_container_init() 2007-10-19 11:53:37 -07:00
highmem.c [MIPS] Remove LIMITED_DMA support 2007-05-11 14:28:31 +01:00
init.c [MIPS] Fix aliasing bug in copy_user_highpage, take 2. 2007-10-16 18:23:49 +01:00
ioremap.c Detach sched.h from mm.h 2007-05-21 09:18:19 -07:00
Makefile [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
pg-r4k.c [MIPS] Allow hardwiring of the CPU type to a single type for optimization. 2007-10-11 23:46:15 +01:00
pg-sb1.c [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
pgtable-32.c [MIPS] Add external declaration of pagetable_init() to pgalloc.h 2007-02-18 21:31:36 +00:00
pgtable-64.c [MIPS] Add external declaration of pagetable_init() to pgalloc.h 2007-02-18 21:31:36 +00:00
pgtable.c [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
sc-ip22.c
sc-mips.c [MIPS] Fix "no space between function name and open parenthesis" warnings. 2007-10-11 23:46:15 +01:00
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c [MIPS] Fix "no space between function name and open parenthesis" warnings. 2007-10-11 23:46:15 +01:00
tlb-r8k.c [MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11 23:46:15 +01:00
tlbex-fault.S [MIPS] Stacktrace build-fix and improvement 2006-10-01 23:16:58 +01:00
tlbex.c [MIPS] Revert "[MIPS] tlbex.c: Cleanup __init usage." 2007-10-13 00:53:00 +01:00