forked from Minki/linux
90303b1023
Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
332 lines
6.7 KiB
ArmAsm
332 lines
6.7 KiB
ArmAsm
/*
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* linux/arch/arm/lib/csumpartialcopygeneric.S
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*
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* Copyright (C) 1995-2001 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* unsigned int
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* csum_partial_copy_xxx(const char *src, char *dst, int len, int sum, )
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* r0 = src, r1 = dst, r2 = len, r3 = sum
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* Returns : r0 = checksum
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*
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* Note that 'tst' and 'teq' preserve the carry flag.
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*/
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src .req r0
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dst .req r1
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len .req r2
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sum .req r3
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.Lzero: mov r0, sum
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load_regs
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/*
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* Align an unaligned destination pointer. We know that
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* we have >= 8 bytes here, so we don't need to check
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* the length. Note that the source pointer hasn't been
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* aligned yet.
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*/
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.Ldst_unaligned:
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tst dst, #1
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beq .Ldst_16bit
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load1b ip
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sub len, len, #1
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adcs sum, sum, ip, put_byte_1 @ update checksum
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strb ip, [dst], #1
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tst dst, #2
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moveq pc, lr @ dst is now 32bit aligned
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.Ldst_16bit: load2b r8, ip
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sub len, len, #2
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adcs sum, sum, r8, put_byte_0
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strb r8, [dst], #1
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adcs sum, sum, ip, put_byte_1
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strb ip, [dst], #1
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mov pc, lr @ dst is now 32bit aligned
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/*
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* Handle 0 to 7 bytes, with any alignment of source and
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* destination pointers. Note that when we get here, C = 0
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*/
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.Lless8: teq len, #0 @ check for zero count
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beq .Lzero
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/* we must have at least one byte. */
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tst dst, #1 @ dst 16-bit aligned
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beq .Lless8_aligned
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/* Align dst */
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load1b ip
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sub len, len, #1
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adcs sum, sum, ip, put_byte_1 @ update checksum
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strb ip, [dst], #1
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tst len, #6
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beq .Lless8_byteonly
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1: load2b r8, ip
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sub len, len, #2
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adcs sum, sum, r8, put_byte_0
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strb r8, [dst], #1
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adcs sum, sum, ip, put_byte_1
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strb ip, [dst], #1
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.Lless8_aligned:
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tst len, #6
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bne 1b
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.Lless8_byteonly:
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tst len, #1
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beq .Ldone
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load1b r8
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adcs sum, sum, r8, put_byte_0 @ update checksum
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strb r8, [dst], #1
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b .Ldone
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FN_ENTRY
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save_regs
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cmp len, #8 @ Ensure that we have at least
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blo .Lless8 @ 8 bytes to copy.
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adds sum, sum, #0 @ C = 0
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tst dst, #3 @ Test destination alignment
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blne .Ldst_unaligned @ align destination, return here
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/*
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* Ok, the dst pointer is now 32bit aligned, and we know
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* that we must have more than 4 bytes to copy. Note
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* that C contains the carry from the dst alignment above.
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*/
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tst src, #3 @ Test source alignment
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bne .Lsrc_not_aligned
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/* Routine for src & dst aligned */
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bics ip, len, #15
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beq 2f
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1: load4l r4, r5, r6, r7
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stmia dst!, {r4, r5, r6, r7}
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adcs sum, sum, r4
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adcs sum, sum, r5
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adcs sum, sum, r6
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adcs sum, sum, r7
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sub ip, ip, #16
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teq ip, #0
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bne 1b
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2: ands ip, len, #12
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beq 4f
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tst ip, #8
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beq 3f
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load2l r4, r5
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stmia dst!, {r4, r5}
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adcs sum, sum, r4
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adcs sum, sum, r5
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tst ip, #4
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beq 4f
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3: load1l r4
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str r4, [dst], #4
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adcs sum, sum, r4
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4: ands len, len, #3
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beq .Ldone
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load1l r4
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tst len, #2
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mov r5, r4, get_byte_0
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beq .Lexit
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adcs sum, sum, r4, push #16
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strb r5, [dst], #1
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mov r5, r4, get_byte_1
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strb r5, [dst], #1
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mov r5, r4, get_byte_2
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.Lexit: tst len, #1
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strneb r5, [dst], #1
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andne r5, r5, #255
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adcnes sum, sum, r5, put_byte_0
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/*
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* If the dst pointer was not 16-bit aligned, we
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* need to rotate the checksum here to get around
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* the inefficient byte manipulations in the
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* architecture independent code.
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*/
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.Ldone: adc r0, sum, #0
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ldr sum, [sp, #0] @ dst
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tst sum, #1
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movne r0, r0, ror #8
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load_regs
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.Lsrc_not_aligned:
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adc sum, sum, #0 @ include C from dst alignment
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and ip, src, #3
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bic src, src, #3
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load1l r5
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cmp ip, #2
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beq .Lsrc2_aligned
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bhi .Lsrc3_aligned
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mov r4, r5, pull #8 @ C = 0
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bics ip, len, #15
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beq 2f
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1: load4l r5, r6, r7, r8
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orr r4, r4, r5, push #24
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mov r5, r5, pull #8
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orr r5, r5, r6, push #24
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mov r6, r6, pull #8
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orr r6, r6, r7, push #24
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mov r7, r7, pull #8
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orr r7, r7, r8, push #24
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stmia dst!, {r4, r5, r6, r7}
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adcs sum, sum, r4
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adcs sum, sum, r5
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adcs sum, sum, r6
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adcs sum, sum, r7
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mov r4, r8, pull #8
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sub ip, ip, #16
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teq ip, #0
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bne 1b
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2: ands ip, len, #12
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beq 4f
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tst ip, #8
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beq 3f
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load2l r5, r6
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orr r4, r4, r5, push #24
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mov r5, r5, pull #8
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orr r5, r5, r6, push #24
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stmia dst!, {r4, r5}
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adcs sum, sum, r4
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adcs sum, sum, r5
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mov r4, r6, pull #8
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tst ip, #4
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beq 4f
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3: load1l r5
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orr r4, r4, r5, push #24
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str r4, [dst], #4
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adcs sum, sum, r4
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mov r4, r5, pull #8
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4: ands len, len, #3
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beq .Ldone
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mov r5, r4, get_byte_0
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tst len, #2
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beq .Lexit
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adcs sum, sum, r4, push #16
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strb r5, [dst], #1
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mov r5, r4, get_byte_1
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strb r5, [dst], #1
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mov r5, r4, get_byte_2
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b .Lexit
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.Lsrc2_aligned: mov r4, r5, pull #16
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adds sum, sum, #0
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bics ip, len, #15
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beq 2f
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1: load4l r5, r6, r7, r8
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orr r4, r4, r5, push #16
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mov r5, r5, pull #16
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orr r5, r5, r6, push #16
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mov r6, r6, pull #16
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orr r6, r6, r7, push #16
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mov r7, r7, pull #16
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orr r7, r7, r8, push #16
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stmia dst!, {r4, r5, r6, r7}
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adcs sum, sum, r4
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adcs sum, sum, r5
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adcs sum, sum, r6
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adcs sum, sum, r7
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mov r4, r8, pull #16
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sub ip, ip, #16
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teq ip, #0
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bne 1b
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2: ands ip, len, #12
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beq 4f
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tst ip, #8
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beq 3f
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load2l r5, r6
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orr r4, r4, r5, push #16
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mov r5, r5, pull #16
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orr r5, r5, r6, push #16
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stmia dst!, {r4, r5}
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adcs sum, sum, r4
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adcs sum, sum, r5
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mov r4, r6, pull #16
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tst ip, #4
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beq 4f
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3: load1l r5
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orr r4, r4, r5, push #16
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str r4, [dst], #4
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adcs sum, sum, r4
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mov r4, r5, pull #16
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4: ands len, len, #3
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beq .Ldone
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mov r5, r4, get_byte_0
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tst len, #2
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beq .Lexit
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adcs sum, sum, r4
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strb r5, [dst], #1
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mov r5, r4, get_byte_1
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strb r5, [dst], #1
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tst len, #1
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beq .Ldone
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load1b r5
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b .Lexit
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.Lsrc3_aligned: mov r4, r5, pull #24
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adds sum, sum, #0
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bics ip, len, #15
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beq 2f
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1: load4l r5, r6, r7, r8
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orr r4, r4, r5, push #8
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mov r5, r5, pull #24
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orr r5, r5, r6, push #8
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mov r6, r6, pull #24
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orr r6, r6, r7, push #8
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mov r7, r7, pull #24
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orr r7, r7, r8, push #8
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stmia dst!, {r4, r5, r6, r7}
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adcs sum, sum, r4
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adcs sum, sum, r5
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adcs sum, sum, r6
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adcs sum, sum, r7
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mov r4, r8, pull #24
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sub ip, ip, #16
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teq ip, #0
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bne 1b
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2: ands ip, len, #12
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beq 4f
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tst ip, #8
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beq 3f
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load2l r5, r6
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orr r4, r4, r5, push #8
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mov r5, r5, pull #24
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orr r5, r5, r6, push #8
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stmia dst!, {r4, r5}
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adcs sum, sum, r4
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adcs sum, sum, r5
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mov r4, r6, pull #24
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tst ip, #4
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beq 4f
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3: load1l r5
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orr r4, r4, r5, push #8
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str r4, [dst], #4
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adcs sum, sum, r4
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mov r4, r5, pull #24
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4: ands len, len, #3
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beq .Ldone
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mov r5, r4, get_byte_0
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tst len, #2
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beq .Lexit
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strb r5, [dst], #1
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adcs sum, sum, r4
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load1l r4
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mov r5, r4, get_byte_0
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strb r5, [dst], #1
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adcs sum, sum, r4, push #24
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mov r5, r4, get_byte_1
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b .Lexit
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