linux/drivers/gpu/drm/amd/include
Likun Gao 2a53291ef2 drm/amdgpu: add SMUIO 11.0.6 register headers
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09 15:28:11 -05:00
..
asic_reg drm/amdgpu: add SMUIO 11.0.6 register headers 2021-02-09 15:28:11 -05:00
ivsrcid drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) 2020-06-03 13:52:03 -04:00
amd_acpi.h
amd_pcie_helpers.h
amd_pcie.h drm/amdgpu:Add pcie gen5 support in pcie capability. 2021-01-21 09:54:56 -05:00
amd_shared.h drm/amd/pm: enable DCS 2021-02-09 15:27:57 -05:00
arct_ip_offset.h drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h drm/amd/pm: correct VR shared rail info 2020-10-27 11:58:57 -04:00
atomfirmware.h drm/amdgpu: new macro for determining 2ND_USB20PORT support 2020-12-10 16:41:49 -05:00
atomfirmwareid.h
cgs_common.h
cik_structs.h
dimgrey_cavefish_ip_offset.h drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
discovery.h
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h drm next for 5.10-rc1 2020-10-15 10:46:16 -07:00
kgd_pp_interface.h drm/amd/pm: implement processor fine grain feature for vangogh (v3) 2021-01-13 23:52:58 -05:00
navi10_enum.h
navi10_ip_offset.h drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi12_ip_offset.h drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi14_ip_offset.h drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
pptable.h
renoir_ip_offset.h drm/amd/include/renoir_ip_offset: Mark top-level IP_BASE as __maybe_unused 2021-01-14 13:20:20 -05:00
sienna_cichlid_ip_offset.h drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
soc15_hw_ip.h
soc15_ih_clientid.h drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid 2020-06-03 13:52:04 -04:00
v9_structs.h
v10_structs.h
vangogh_ip_offset.h drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
vega10_enum.h
vega10_ip_offset.h drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused 2020-11-13 17:29:46 -05:00
vega20_ip_offset.h drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
vi_structs.h