forked from Minki/linux
1e17de9049
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
/*
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* Copyright (c) 2015 Linaro Ltd.
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* Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include "clk-mtk.h"
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#include "clk-cpumux.h"
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static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
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{
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return container_of(_hw, struct mtk_clk_cpumux, hw);
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}
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static u8 clk_cpumux_get_parent(struct clk_hw *hw)
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{
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struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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unsigned int val;
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regmap_read(mux->regmap, mux->reg, &val);
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val >>= mux->shift;
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val &= mux->mask;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
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u32 mask, val;
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val = index << mux->shift;
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mask = mux->mask << mux->shift;
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return regmap_update_bits(mux->regmap, mux->reg, mask, val);
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}
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static const struct clk_ops clk_cpumux_ops = {
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.get_parent = clk_cpumux_get_parent,
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.set_parent = clk_cpumux_set_parent,
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};
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static struct clk __init *
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mtk_clk_register_cpumux(const struct mtk_composite *mux,
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struct regmap *regmap)
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{
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struct mtk_clk_cpumux *cpumux;
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struct clk *clk;
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struct clk_init_data init;
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cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
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if (!cpumux)
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return ERR_PTR(-ENOMEM);
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init.name = mux->name;
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init.ops = &clk_cpumux_ops;
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init.parent_names = mux->parent_names;
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init.num_parents = mux->num_parents;
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init.flags = mux->flags;
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cpumux->reg = mux->mux_reg;
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cpumux->shift = mux->mux_shift;
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cpumux->mask = BIT(mux->mux_width) - 1;
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cpumux->regmap = regmap;
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cpumux->hw.init = &init;
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clk = clk_register(NULL, &cpumux->hw);
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if (IS_ERR(clk))
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kfree(cpumux);
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return clk;
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}
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int __init mtk_clk_register_cpumuxes(struct device_node *node,
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const struct mtk_composite *clks, int num,
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struct clk_onecell_data *clk_data)
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{
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int i;
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struct clk *clk;
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struct regmap *regmap;
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regmap = syscon_node_to_regmap(node);
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if (IS_ERR(regmap)) {
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pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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for (i = 0; i < num; i++) {
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const struct mtk_composite *mux = &clks[i];
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clk = mtk_clk_register_cpumux(mux, regmap);
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if (IS_ERR(clk)) {
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pr_err("Failed to register clk %s: %ld\n",
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mux->name, PTR_ERR(clk));
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continue;
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}
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clk_data->clks[mux->id] = clk;
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}
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return 0;
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}
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