forked from Minki/linux
305524902a
Add the Microchip lan966x ethernet serdes PHY driver for interfaces available in the lan966x SoC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211116100818.1615762-4-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
210 lines
7.0 KiB
C
210 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _LAN966X_SERDES_REGS_H_
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#define _LAN966X_SERDES_REGS_H_
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include <linux/bug.h>
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enum lan966x_target {
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TARGET_HSIO = 32,
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NUM_TARGETS = 66
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};
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#define __REG(...) __VA_ARGS__
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/* HSIO:SD:SD_CFG */
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#define HSIO_SD_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)
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#define HSIO_SD_CFG_PHY_RESET BIT(27)
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#define HSIO_SD_CFG_PHY_RESET_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
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#define HSIO_SD_CFG_PHY_RESET_GET(x)\
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FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
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#define HSIO_SD_CFG_TX_RESET BIT(18)
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#define HSIO_SD_CFG_TX_RESET_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
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#define HSIO_SD_CFG_TX_RESET_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
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#define HSIO_SD_CFG_TX_RATE GENMASK(17, 16)
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#define HSIO_SD_CFG_TX_RATE_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
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#define HSIO_SD_CFG_TX_RATE_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_RATE, x)
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#define HSIO_SD_CFG_TX_INVERT BIT(15)
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#define HSIO_SD_CFG_TX_INVERT_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
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#define HSIO_SD_CFG_TX_INVERT_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)
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#define HSIO_SD_CFG_TX_EN BIT(14)
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#define HSIO_SD_CFG_TX_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
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#define HSIO_SD_CFG_TX_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_EN, x)
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#define HSIO_SD_CFG_TX_DATA_EN BIT(12)
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#define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
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#define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)
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#define HSIO_SD_CFG_TX_CM_EN BIT(11)
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#define HSIO_SD_CFG_TX_CM_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
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#define HSIO_SD_CFG_TX_CM_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)
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#define HSIO_SD_CFG_LANE_10BIT_SEL BIT(10)
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#define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
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#define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
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FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)
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#define HSIO_SD_CFG_RX_TERM_EN BIT(9)
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#define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
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#define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)
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#define HSIO_SD_CFG_RX_RESET BIT(8)
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#define HSIO_SD_CFG_RX_RESET_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
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#define HSIO_SD_CFG_RX_RESET_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_RESET, x)
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#define HSIO_SD_CFG_RX_RATE GENMASK(7, 6)
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#define HSIO_SD_CFG_RX_RATE_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
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#define HSIO_SD_CFG_RX_RATE_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_RATE, x)
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#define HSIO_SD_CFG_RX_PLL_EN BIT(5)
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#define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
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#define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)
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#define HSIO_SD_CFG_RX_INVERT BIT(3)
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#define HSIO_SD_CFG_RX_INVERT_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
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#define HSIO_SD_CFG_RX_INVERT_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)
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#define HSIO_SD_CFG_RX_DATA_EN BIT(2)
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#define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
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#define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)
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#define HSIO_SD_CFG_LANE_LOOPBK_EN BIT(0)
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#define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
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FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
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#define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
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FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
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/* HSIO:SD:MPLL_CFG */
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#define HSIO_MPLL_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)
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#define HSIO_MPLL_CFG_REF_SSP_EN BIT(18)
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#define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
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FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
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#define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
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FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)
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#define HSIO_MPLL_CFG_REF_CLKDIV2 BIT(17)
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#define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
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FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
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#define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
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FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)
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#define HSIO_MPLL_CFG_MPLL_EN BIT(16)
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#define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
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FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
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#define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
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FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)
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#define HSIO_MPLL_CFG_MPLL_MULTIPLIER GENMASK(6, 0)
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#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
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FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
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#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
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FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
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/* HSIO:SD:SD_STAT */
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#define HSIO_SD_STAT(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)
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#define HSIO_SD_STAT_MPLL_STATE BIT(6)
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#define HSIO_SD_STAT_MPLL_STATE_SET(x)\
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FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
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#define HSIO_SD_STAT_MPLL_STATE_GET(x)\
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FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)
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#define HSIO_SD_STAT_TX_STATE BIT(5)
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#define HSIO_SD_STAT_TX_STATE_SET(x)\
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FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
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#define HSIO_SD_STAT_TX_STATE_GET(x)\
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FIELD_GET(HSIO_SD_STAT_TX_STATE, x)
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#define HSIO_SD_STAT_TX_CM_STATE BIT(2)
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#define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
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FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
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#define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
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FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)
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#define HSIO_SD_STAT_RX_PLL_STATE BIT(0)
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#define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
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FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
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#define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
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FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)
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/* HSIO:HW_CFGSTAT:HW_CFG */
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#define HSIO_HW_CFG __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)
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#define HSIO_HW_CFG_RGMII_1_CFG BIT(15)
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#define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
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(((x) << 15) & GENMASK(15, 15))
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#define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
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FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)
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#define HSIO_HW_CFG_RGMII_0_CFG BIT(14)
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#define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
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(((x) << 14) & GENMASK(14, 14))
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#define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
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FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)
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#define HSIO_HW_CFG_RGMII_ENA GENMASK(13, 12)
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#define HSIO_HW_CFG_RGMII_ENA_SET(x)\
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(((x) << 12) & GENMASK(13, 12))
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#define HSIO_HW_CFG_RGMII_ENA_GET(x)\
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FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)
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#define HSIO_HW_CFG_SD6G_0_CFG BIT(11)
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#define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
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(((x) << 11) & GENMASK(11, 11))
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#define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
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FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)
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#define HSIO_HW_CFG_SD6G_1_CFG BIT(10)
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#define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
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(((x) << 10) & GENMASK(10, 10))
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#define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
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FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)
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#define HSIO_HW_CFG_GMII_ENA GENMASK(9, 2)
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#define HSIO_HW_CFG_GMII_ENA_SET(x)\
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(((x) << 2) & GENMASK(9, 2))
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#define HSIO_HW_CFG_GMII_ENA_GET(x)\
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FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)
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#define HSIO_HW_CFG_QSGMII_ENA GENMASK(1, 0)
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#define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
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((x) & GENMASK(1, 0))
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#define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
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FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
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#endif /* _LAN966X_HSIO_REGS_H_ */
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