06f34e1c28
We used to calculate page address differently in 2 cases: 1. In virt_to_page(x) we do --->8--- mem_map + (x - CONFIG_LINUX_LINK_BASE) >> PAGE_SHIFT --->8--- 2. In in pte_page(x) we do --->8--- mem_map + (pte_val(x) - PAGE_OFFSET) >> PAGE_SHIFT --->8--- That leads to problems in case PAGE_OFFSET != CONFIG_LINUX_LINK_BASE - different pages will be selected depending on where and how we calculate page address. In particular in the STAR 9000853582 when gdb attempted to read memory of another process it got improper page in get_user_pages() because this is exactly one of the places where we search for a page by pte_page(). The fix is trivial - we need to calculate page address similarly in both cases. Cc: <stable@vger.kernel.org> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
400 lines
14 KiB
C
400 lines
14 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011
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* -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
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* They are semantically the same although in different contexts
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* VALID marks a TLB entry exists and it will only happen if PRESENT
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* - Utilise some unused free bits to confine PTE flags to 12 bits
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* This is a must for 4k pg-sz
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*
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* vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods
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* -TLB Locking never really existed, except for initial specs
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* -SILENT_xxx not needed for our port
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* -Per my request, MMU V3 changes the layout of some of the bits
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* to avoid a few shifts in TLB Miss handlers.
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*
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* vineetg: April 2010
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* -PGD entry no longer contains any flags. If empty it is 0, otherwise has
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* Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
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*
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* vineetg: April 2010
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* -Switched form 8:11:13 split for page table lookup to 11:8:13
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* -this speeds up page table allocation itself as we now have to memset 1K
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* instead of 8k per page table.
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* -TODO: Right now page table alloc is 8K and rest 7K is unused
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* need to optimise it
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*
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* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
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*/
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#ifndef _ASM_ARC_PGTABLE_H
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#define _ASM_ARC_PGTABLE_H
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm-generic/pgtable-nopmd.h>
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/**************************************************************************
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* Page Table Flags
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*
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* ARC700 MMU only deals with softare managed TLB entries.
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* Page Tables are purely for Linux VM's consumption and the bits below are
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* suited to that (uniqueness). Hence some are not implemented in the TLB and
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* some have different value in TLB.
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* e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in
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* seperate PD0 and PD1, which combined forms a translation entry)
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* while for PTE perspective, they are 8 and 9 respectively
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* with MMU v3: Most bits (except SHARED) represent the exact hardware pos
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* (saves some bit shift ops in TLB Miss hdlrs)
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*/
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#if (CONFIG_ARC_MMU_VER <= 2)
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#define _PAGE_ACCESSED (1<<1) /* Page is accessed (S) */
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#define _PAGE_CACHEABLE (1<<2) /* Page is cached (H) */
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#define _PAGE_EXECUTE (1<<3) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<4) /* Page has user write perm (H) */
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#define _PAGE_READ (1<<5) /* Page has user read perm (H) */
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#define _PAGE_MODIFIED (1<<6) /* Page modified (dirty) (S) */
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#define _PAGE_FILE (1<<7) /* page cache/ swap (S) */
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<10) /* TLB entry is valid (H) */
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#else /* MMU v3 onwards */
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#define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */
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#define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */
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#define _PAGE_READ (1<<3) /* Page has user read perm (H) */
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#define _PAGE_ACCESSED (1<<4) /* Page is accessed (S) */
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#define _PAGE_MODIFIED (1<<5) /* Page modified (dirty) (S) */
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#define _PAGE_FILE (1<<6) /* page cache/ swap (S) */
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
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#define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
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usable for shared TLB entries (H) */
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#endif
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/* vmalloc permissions */
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#define _K_PAGE_PERMS (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
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_PAGE_GLOBAL | _PAGE_PRESENT)
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#ifdef CONFIG_ARC_CACHE_PAGES
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#define _PAGE_DEF_CACHEABLE _PAGE_CACHEABLE
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#else
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#define _PAGE_DEF_CACHEABLE (0)
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#endif
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/* Helper for every "user" page
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* -kernel can R/W/X
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* -by default cached, unless config otherwise
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* -present in memory
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*/
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#define ___DEF (_PAGE_PRESENT | _PAGE_DEF_CACHEABLE)
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/* Set of bits not changed in pte_modify */
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
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/* More Abbrevaited helpers */
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#define PAGE_U_NONE __pgprot(___DEF)
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#define PAGE_U_R __pgprot(___DEF | _PAGE_READ)
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#define PAGE_U_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
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#define PAGE_U_X_R __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
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#define PAGE_U_X_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE | \
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_PAGE_EXECUTE)
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#define PAGE_SHARED PAGE_U_W_R
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/* While kernel runs out of unstranslated space, vmalloc/modules use a chunk of
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* user vaddr space - visible in all addr spaces, but kernel mode only
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* Thus Global, all-kernel-access, no-user-access, cached
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*/
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#define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_DEF_CACHEABLE)
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/* ioremap */
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#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
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/* Masks for actual TLB "PD"s */
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#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
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#define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
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#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE)
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/**************************************************************************
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* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
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*
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* Certain cases have 1:1 mapping
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* e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
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* which directly corresponds to PAGE_U_X_R
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*
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* Other rules which cause the divergence from 1:1 mapping
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*
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* 1. Although ARC700 can do exclusive execute/write protection (meaning R
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* can be tracked independet of X/W unlike some other CPUs), still to
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* keep things consistent with other archs:
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* -Write implies Read: W => R
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* -Execute implies Read: X => R
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*
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* 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
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* This is to enable COW mechanism
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*/
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/* xwr */
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#define __P000 PAGE_U_NONE
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#define __P001 PAGE_U_R
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#define __P010 PAGE_U_R /* Pvt-W => !W */
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#define __P011 PAGE_U_R /* Pvt-W => !W */
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#define __P100 PAGE_U_X_R /* X => R */
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#define __P101 PAGE_U_X_R
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#define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
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#define __P111 PAGE_U_X_R /* Pvt-W => !W */
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#define __S000 PAGE_U_NONE
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#define __S001 PAGE_U_R
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#define __S010 PAGE_U_W_R /* W => R */
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#define __S011 PAGE_U_W_R
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#define __S100 PAGE_U_X_R /* X => R */
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#define __S101 PAGE_U_X_R
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#define __S110 PAGE_U_X_W_R /* X => R */
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#define __S111 PAGE_U_X_W_R
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/****************************************************************
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* Page Table Lookup split
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*
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* We implement 2 tier paging and since this is all software, we are free
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* to customize the span of a PGD / PTE entry to suit us
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*
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* 32 bit virtual address
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* -------------------------------------------------------
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* | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE |
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* -------------------------------------------------------
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* | | |
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* | | --> off in page frame
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* | |
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* | ---> index into Page Table
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* |
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* ----> index into Page Directory
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*/
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#define BITS_IN_PAGE PAGE_SHIFT
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/* Optimal Sizing of Pg Tbl - based on MMU page size */
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#if defined(CONFIG_ARC_PAGE_SIZE_8K)
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#define BITS_FOR_PTE 8
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#elif defined(CONFIG_ARC_PAGE_SIZE_16K)
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#define BITS_FOR_PTE 8
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#elif defined(CONFIG_ARC_PAGE_SIZE_4K)
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#define BITS_FOR_PTE 9
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#endif
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#define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE)
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#define PGDIR_SHIFT (BITS_FOR_PTE + BITS_IN_PAGE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#ifdef __ASSEMBLY__
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#define PTRS_PER_PTE (1 << BITS_FOR_PTE)
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#define PTRS_PER_PGD (1 << BITS_FOR_PGD)
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#else
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#define PTRS_PER_PTE (1UL << BITS_FOR_PTE)
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#define PTRS_PER_PGD (1UL << BITS_FOR_PGD)
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#endif
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/*
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* Number of entries a user land program use.
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* TASK_SIZE is the maximum vaddr that can be used by a userland program.
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*/
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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/*
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* No special requirements for lowest virtual address we permit any user space
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* mapping to be mapped at.
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*/
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#define FIRST_USER_ADDRESS 0
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/****************************************************************
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* Bucket load of VM Helpers
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*/
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#ifndef __ASSEMBLY__
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#define pte_ERROR(e) \
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pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pgd_ERROR(e) \
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pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/* the zero page used for uninitialized and anonymous pages */
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extern char empty_zero_page[PAGE_SIZE];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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/* find the page descriptor of the Page Tbl ref by PMD entry */
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#define pmd_page(pmd) virt_to_page(pmd_val(pmd) & PAGE_MASK)
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/* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
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#define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
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/* In a 2 level sys, setup the PGD entry with PTE value */
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static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
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{
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pmd_val(*pmdp) = (unsigned long)ptep;
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}
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm, addr, ptep) set_pte_at(mm, addr, ptep, __pte(0))
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
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#define pmd_present(x) (pmd_val(x))
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#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
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#define pte_page(x) (mem_map + \
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(unsigned long)(((pte_val(x) - CONFIG_LINUX_LINK_BASE) >> \
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PAGE_SHIFT)))
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#define mk_pte(page, pgprot) \
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({ \
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pte_t pte; \
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pte_val(pte) = __pa(page_address(page)) + pgprot_val(pgprot); \
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pte; \
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})
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/* TBD: Non linear mapping stuff */
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static inline int pte_file(pte_t pte)
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{
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return pte_val(pte) & _PAGE_FILE;
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}
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#define PTE_FILE_MAX_BITS 30
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#define pgoff_to_pte(x) __pte(x)
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#define pte_to_pgoff(x) (pte_val(x) >> 2)
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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/*
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* pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
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* and returns ptr to PTE entry corresponding to @addr
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*/
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#define pte_offset(dir, addr) ((pte_t *)(pmd_page_vaddr(*dir)) +\
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__pte_index(addr))
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/* No mapping of Page Tables in high mem etc, so following same as above */
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#define pte_offset_kernel(dir, addr) pte_offset(dir, addr)
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#define pte_offset_map(dir, addr) pte_offset(dir, addr)
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/* Zoo of pte_xxx function */
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#define pte_read(pte) (pte_val(pte) & _PAGE_READ)
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#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
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#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
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#define pte_special(pte) (0)
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#define PTE_BIT_FUNC(fn, op) \
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static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
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PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
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PTE_BIT_FUNC(mkwrite, |= (_PAGE_WRITE));
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PTE_BIT_FUNC(mkclean, &= ~(_PAGE_MODIFIED));
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PTE_BIT_FUNC(mkdirty, |= (_PAGE_MODIFIED));
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PTE_BIT_FUNC(mkold, &= ~(_PAGE_ACCESSED));
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PTE_BIT_FUNC(mkyoung, |= (_PAGE_ACCESSED));
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PTE_BIT_FUNC(exprotect, &= ~(_PAGE_EXECUTE));
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PTE_BIT_FUNC(mkexec, |= (_PAGE_EXECUTE));
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/* Macro to mark a page protection as uncacheable */
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#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pteval)
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{
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set_pte(ptep, pteval);
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}
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/*
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* All kernel related VM pages are in init's mm.
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*/
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
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#define pgd_offset(mm, addr) (((mm)->pgd)+pgd_index(addr))
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/*
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* Macro to quickly access the PGD entry, utlising the fact that some
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* arch may cache the pointer to Page Directory of "current" task
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* in a MMU register
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*
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* Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
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* becomes read a register
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*
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* ********CAUTION*******:
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* Kernel code might be dealing with some mm_struct of NON "current"
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* Thus use this macro only when you are certain that "current" is current
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* e.g. when dealing with signal frame setup code etc
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*/
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#ifndef CONFIG_SMP
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#define pgd_offset_fast(mm, addr) \
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({ \
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pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
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pgd_base + pgd_index(addr); \
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})
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#else
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#define pgd_offset_fast(mm, addr) pgd_offset(mm, addr)
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#endif
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extern void paging_init(void);
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extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep);
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/* Encode swap {type,off} tuple into PTE
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* We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
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* both PAGE_FILE and PAGE_PRESENT are zero in a PTE holding swap "identifier"
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*/
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#define __swp_entry(type, off) ((swp_entry_t) { \
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((type) & 0x1f) | ((off) << 13) })
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/* Decode a PTE containing swap "identifier "into constituents */
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#define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f)
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#define __swp_offset(pte_lookalike) ((pte_lookalike).val << 13)
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/* NOPs, to keep generic kernel happy */
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define kern_addr_valid(addr) (1)
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/*
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* remap a physical page `pfn' of size `size' with page protection `prot'
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* into virtual address `from'
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*/
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#include <asm-generic/pgtable.h>
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/* to cope with aliasing VIPT cache */
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#define HAVE_ARCH_UNMAPPED_AREA
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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#endif /* __ASSEMBLY__ */
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#endif
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