forked from Minki/linux
9dff67333a
Hang the three switches of the three MDIO busses using the new DSA binding. Also, make use of the mdio-bus and explicitly list the phys on one device. This is not required, but good for testing. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
747 lines
15 KiB
Plaintext
747 lines
15 KiB
Plaintext
/*
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* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
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*
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* Based on an original 'vf610-twr.dts' which is Copyright 2015,
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* Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "ZII VF610 Development Board, Rev B";
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compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pinctrl_leds_debug>;
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pinctrl-names = "default";
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debug {
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label = "zii:green:debug1";
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gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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mdio-mux {
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compatible = "mdio-mux-gpio";
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pinctrl-0 = <&pinctrl_mdio_mux>;
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pinctrl-names = "default";
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gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
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&gpio0 9 GPIO_ACTIVE_HIGH
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&gpio0 24 GPIO_ACTIVE_HIGH
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&gpio0 25 GPIO_ACTIVE_HIGH>;
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mdio-parent-bus = <&mdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_mux_1: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch0@0 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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switch0port5: port@5 {
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reg = <5>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch1port6
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&switch2port9>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&fec1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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};
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};
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mdio_mux_2: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch1: switch1@0 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-handle = <&switch1phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&switch1phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan5";
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phy-handle = <&switch1phy2>;
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};
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switch1port5: port@5 {
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reg = <5>;
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label = "dsa";
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link = <&switch2port9>;
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phy-mode = "rgmii-txid";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch1port6: port@6 {
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reg = <6>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch0port5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch1phy0: switch1phy0@0 {
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reg = <0>;
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};
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switch1phy1: switch1phy0@1 {
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reg = <1>;
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};
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switch1phy2: switch1phy0@2 {
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reg = <2>;
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};
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};
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};
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};
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mdio_mux_4: mdio@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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switch2: switch2@0 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan6";
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};
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port@1 {
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reg = <1>;
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label = "lan7";
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};
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port@2 {
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reg = <2>;
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label = "lan8";
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};
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port@3 {
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reg = <3>;
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label = "optical3";
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fixed-link {
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speed = <1000>;
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full-duplex;
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link-gpios = <&gpio6 2
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GPIO_ACTIVE_HIGH>;
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};
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};
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port@4 {
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reg = <4>;
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label = "optical4";
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fixed-link {
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speed = <1000>;
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full-duplex;
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link-gpios = <&gpio6 3
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GPIO_ACTIVE_HIGH>;
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};
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};
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switch2port9: port@9 {
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reg = <9>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch1port5
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&switch0port5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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mdio_mux_8: mdio@8 {
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reg = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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usb0_vbus: regulator-usb0-vbus {
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compatible = "regulator-fixed";
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pinctrl-0 = <&pinctrl_usb_vbus>;
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 6 0>;
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};
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spi0 {
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compatible = "spi-gpio";
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pinctrl-0 = <&pinctrl_gpio_spi0>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
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&gpio1 8 GPIO_ACTIVE_HIGH>;
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num-chipselects = <2>;
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m25p128@0 {
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compatible = "m25p128", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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at93c46d@1 {
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compatible = "atmel,at93c46d";
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pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
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pinctrl-names = "default";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <1>;
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spi-max-frequency = <500000>;
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spi-cs-high;
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data-size = <16>;
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select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&adc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0_ad5>;
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&edma0 {
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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status = "okay";
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};
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&fec0 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec0>;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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gpio5: pca9554@20 {
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compatible = "nxp,pca9554";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio6: pca9554@22 {
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compatible = "nxp,pca9554";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9554_22>;
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio2>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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};
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lm75@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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at24c04@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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at24c04@52 {
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compatible = "atmel,24c04";
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reg = <0x52>;
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};
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ds1682@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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tca9548@70 {
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compatible = "nxp,pca9548";
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pinctrl-0 = <&pinctrl_i2c_mux_reset>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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sfp1: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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sfp2: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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sfp3: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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sfp4: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbdev0 {
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disable-over-current;
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vbus-supply = <&usb0_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbmisc0 {
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status = "okay";
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};
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&usbmisc1 {
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status = "okay";
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};
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&usbphy0 {
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_adc0_ad5: adc0ad5grp {
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fsl,pins = <
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VF610_PAD_PTC30__ADC0_SE5 0x00a1
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>;
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};
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|
pinctrl_dspi0: dspi0grp {
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fsl,pins = <
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VF610_PAD_PTB18__DSPI0_CS1 0x1182
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VF610_PAD_PTB19__DSPI0_CS0 0x1182
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VF610_PAD_PTB20__DSPI0_SIN 0x1181
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VF610_PAD_PTB21__DSPI0_SOUT 0x1182
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VF610_PAD_PTB22__DSPI0_SCK 0x1182
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>;
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};
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|
|
pinctrl_dspi2: dspi2grp {
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fsl,pins = <
|
|
VF610_PAD_PTD31__DSPI2_CS1 0x1182
|
|
VF610_PAD_PTD30__DSPI2_CS0 0x1182
|
|
VF610_PAD_PTD29__DSPI2_SIN 0x1181
|
|
VF610_PAD_PTD28__DSPI2_SOUT 0x1182
|
|
VF610_PAD_PTD27__DSPI2_SCK 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_esdhc1: esdhc1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
|
|
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
|
|
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
|
|
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
|
|
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
|
|
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
|
|
VF610_PAD_PTA7__GPIO_134 0x219d
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec0: fec0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
|
|
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
|
|
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
|
|
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
|
|
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
|
|
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
|
|
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
|
|
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
|
|
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec1: fec1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
|
|
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
|
|
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
|
|
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
|
|
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
|
|
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
|
|
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
|
|
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
|
|
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
|
|
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
|
|
fsl,pins = <
|
|
VF610_PAD_PTE27__GPIO_132 0x33e2
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB22__GPIO_44 0x33e2
|
|
VF610_PAD_PTB21__GPIO_43 0x33e2
|
|
VF610_PAD_PTB20__GPIO_42 0x33e1
|
|
VF610_PAD_PTB19__GPIO_41 0x33e2
|
|
VF610_PAD_PTB18__GPIO_40 0x33e2
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
|
|
fsl,pins = <
|
|
VF610_PAD_PTE14__GPIO_119 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c0: i2c0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB14__I2C0_SCL 0x37ff
|
|
VF610_PAD_PTB15__I2C0_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB16__I2C1_SCL 0x37ff
|
|
VF610_PAD_PTB17__I2C1_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA22__I2C2_SCL 0x37ff
|
|
VF610_PAD_PTA23__I2C2_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA30__I2C3_SCL 0x37ff
|
|
VF610_PAD_PTA31__I2C3_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_leds_debug: pinctrl-leds-debug {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD20__GPIO_74 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_mdio_mux: pinctrl-mdio-mux {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA18__GPIO_8 0x31c2
|
|
VF610_PAD_PTA19__GPIO_9 0x31c2
|
|
VF610_PAD_PTB2__GPIO_24 0x31c2
|
|
VF610_PAD_PTB3__GPIO_25 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_pca9554_22: pinctrl-pca95540-22 {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB28__GPIO_98 0x219d
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm0: pwm0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB0__FTM0_CH0 0x1582
|
|
VF610_PAD_PTB1__FTM0_CH1 0x1582
|
|
VF610_PAD_PTB2__FTM0_CH2 0x1582
|
|
VF610_PAD_PTB3__FTM0_CH3 0x1582
|
|
>;
|
|
};
|
|
|
|
pinctrl_qspi0: qspi0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
|
|
VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
|
|
VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
|
|
VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
|
|
VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
|
|
VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart0: uart0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB10__UART0_TX 0x21a2
|
|
VF610_PAD_PTB11__UART0_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB23__UART1_TX 0x21a2
|
|
VF610_PAD_PTB24__UART1_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD0__UART2_TX 0x21a2
|
|
VF610_PAD_PTD1__UART2_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb_vbus: pinctrl-usb-vbus {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA16__GPIO_6 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb0_host: usb0-host-grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD6__GPIO_85 0x0062
|
|
>;
|
|
};
|
|
};
|