forked from Minki/linux
f065e9e4ad
Commit833f2cbf70("ARM: dts: imx6: change the core clock of spdif") changed many more clocks than only the SPDIF core clock as stated in the commit message. The MLB clock has been added and this causes SPDIF regression as reported by Xavi Drudis Ferran and also in this forum post: https://forum.digikey.com/thread/34240 The MX6Q Reference Manual does not mention that MLB is a clock related to SPDIF, so change it back to a dummy clock to restore SPDIF functionality. Thanks to Ambika for providing the fix at: https://community.nxp.com/thread/387131 Fixes:833f2cbf70("ARM: dts: imx6: change the core clock of spdif") Cc: <stable@vger.kernel.org> # 4.4.x Reported-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1282 lines
33 KiB
Plaintext
1282 lines
33 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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aliases {
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ethernet0 = &fec;
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can0 = &can1;
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can1 = &can2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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ipu0 = &ipu1;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mmc3 = &usdhc4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gpc>;
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ranges;
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dma_apbh: dma-apbh@00110000 {
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x00110000 0x2000>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
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};
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gpmi: gpmi-nand@00112000 {
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compatible = "fsl,imx6q-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
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<&clks IMX6QDL_CLK_GPMI_APB>,
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<&clks IMX6QDL_CLK_GPMI_BCH>,
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<&clks IMX6QDL_CLK_GPMI_BCH_APB>,
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<&clks IMX6QDL_CLK_PER1_BCH>;
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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hdmi: hdmi@0120000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
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gpr = <&gpr>;
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clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
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<&clks IMX6QDL_CLK_HDMI_ISFR>;
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clock-names = "iahb", "isfr";
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status = "disabled";
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port@0 {
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reg = <0>;
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
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};
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};
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};
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gpu_3d: gpu@00130000 {
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compatible = "vivante,gc";
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reg = <0x00130000 0x4000>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
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<&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>;
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clock-names = "bus", "core", "shader";
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power-domains = <&gpc 1>;
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};
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gpu_2d: gpu@00134000 {
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compatible = "vivante,gc";
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reg = <0x00134000 0x4000>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>;
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clock-names = "bus", "core";
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power-domains = <&gpc 1>;
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};
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timer@00a00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x00a00600 0x20>;
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interrupts = <1 13 0xf01>;
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interrupt-parent = <&intc>;
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clocks = <&clks IMX6QDL_CLK_TWD>;
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};
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intc: interrupt-controller@00a01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00a01000 0x1000>,
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<0x00a00100 0x100>;
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interrupt-parent = <&intc>;
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};
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L2: l2-cache@00a02000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a02000 0x1000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <4 2 3>;
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arm,data-latency = <4 2 3>;
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arm,shared-override;
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};
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pcie: pcie@0x01000000 {
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x04000>,
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<0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
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<&clks IMX6QDL_CLK_LVDS1_GATE>,
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<&clks IMX6QDL_CLK_PCIE_REF_125M>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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status = "disabled";
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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};
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aips-bus@02000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x100000>;
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ranges;
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spba-bus@02000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x40000>;
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ranges;
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spdif: spdif@02004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
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<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
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<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
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<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
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<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7", "spba";
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status = "disabled";
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};
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ecspi1: ecspi@02008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02008000 0x4000>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ECSPI1>,
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<&clks IMX6QDL_CLK_ECSPI1>;
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clock-names = "ipg", "per";
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dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ecspi2: ecspi@0200c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x0200c000 0x4000>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ECSPI2>,
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<&clks IMX6QDL_CLK_ECSPI2>;
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clock-names = "ipg", "per";
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dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ecspi3: ecspi@02010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02010000 0x4000>;
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interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ECSPI3>,
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<&clks IMX6QDL_CLK_ECSPI3>;
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clock-names = "ipg", "per";
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dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ecspi4: ecspi@02014000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02014000 0x4000>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ECSPI4>,
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<&clks IMX6QDL_CLK_ECSPI4>;
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clock-names = "ipg", "per";
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dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart1: serial@02020000 {
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compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_UART_IPG>,
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<&clks IMX6QDL_CLK_UART_SERIAL>;
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clock-names = "ipg", "per";
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dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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esai: esai@02024000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx35-esai";
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
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<&clks IMX6QDL_CLK_ESAI_MEM>,
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<&clks IMX6QDL_CLK_ESAI_EXTAL>,
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<&clks IMX6QDL_CLK_ESAI_IPG>,
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<&clks IMX6QDL_CLK_SPBA>;
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clock-names = "core", "mem", "extal", "fsys", "spba";
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dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ssi1: ssi@02028000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6q-ssi",
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"fsl,imx51-ssi";
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reg = <0x02028000 0x4000>;
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interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
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<&clks IMX6QDL_CLK_SSI1>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 37 1 0>,
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<&sdma 38 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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ssi2: ssi@0202c000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6q-ssi",
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"fsl,imx51-ssi";
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reg = <0x0202c000 0x4000>;
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interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
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<&clks IMX6QDL_CLK_SSI2>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 41 1 0>,
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<&sdma 42 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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ssi3: ssi@02030000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6q-ssi",
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"fsl,imx51-ssi";
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reg = <0x02030000 0x4000>;
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interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
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<&clks IMX6QDL_CLK_SSI3>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 45 1 0>,
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<&sdma 46 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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asrc: asrc@02034000 {
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compatible = "fsl,imx53-asrc";
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reg = <0x02034000 0x4000>;
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interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
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<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_SPBA>;
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clock-names = "mem", "ipg", "asrck_0",
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"asrck_1", "asrck_2", "asrck_3", "asrck_4",
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"asrck_5", "asrck_6", "asrck_7", "asrck_8",
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"asrck_9", "asrck_a", "asrck_b", "asrck_c",
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"asrck_d", "asrck_e", "asrck_f", "spba";
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dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
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<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
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dma-names = "rxa", "rxb", "rxc",
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"txa", "txb", "txc";
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fsl,asrc-rate = <48000>;
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fsl,asrc-width = <16>;
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status = "okay";
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};
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spba@0203c000 {
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reg = <0x0203c000 0x4000>;
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};
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};
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vpu: vpu@02040000 {
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compatible = "cnm,coda960";
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reg = <0x02040000 0x3c000>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "bit", "jpeg";
|
|
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
|
|
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
|
|
clock-names = "per", "ahb";
|
|
power-domains = <&gpc 1>;
|
|
resets = <&src 1>;
|
|
iram = <&ocram>;
|
|
};
|
|
|
|
aipstz@0207c000 { /* AIPSTZ1 */
|
|
reg = <0x0207c000 0x4000>;
|
|
};
|
|
|
|
pwm1: pwm@02080000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02080000 0x4000>;
|
|
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
<&clks IMX6QDL_CLK_PWM1>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@02084000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02084000 0x4000>;
|
|
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
<&clks IMX6QDL_CLK_PWM2>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@02088000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02088000 0x4000>;
|
|
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
<&clks IMX6QDL_CLK_PWM3>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@0208c000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
|
reg = <0x0208c000 0x4000>;
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
<&clks IMX6QDL_CLK_PWM4>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: flexcan@02090000 {
|
|
compatible = "fsl,imx6q-flexcan";
|
|
reg = <0x02090000 0x4000>;
|
|
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
|
|
<&clks IMX6QDL_CLK_CAN1_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can2: flexcan@02094000 {
|
|
compatible = "fsl,imx6q-flexcan";
|
|
reg = <0x02094000 0x4000>;
|
|
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
|
|
<&clks IMX6QDL_CLK_CAN2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt: gpt@02098000 {
|
|
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
|
reg = <0x02098000 0x4000>;
|
|
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
|
|
<&clks IMX6QDL_CLK_GPT_IPG_PER>,
|
|
<&clks IMX6QDL_CLK_GPT_3M>;
|
|
clock-names = "ipg", "per", "osc_per";
|
|
};
|
|
|
|
gpio1: gpio@0209c000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x0209c000 0x4000>;
|
|
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@020a0000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a0000 0x4000>;
|
|
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@020a4000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a4000 0x4000>;
|
|
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@020a8000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a8000 0x4000>;
|
|
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@020ac000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020ac000 0x4000>;
|
|
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@020b0000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b0000 0x4000>;
|
|
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@020b4000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b4000 0x4000>;
|
|
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
kpp: kpp@020b8000 {
|
|
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
|
|
reg = <0x020b8000 0x4000>;
|
|
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPG>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog1: wdog@020bc000 {
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020bc000 0x4000>;
|
|
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
|
};
|
|
|
|
wdog2: wdog@020c0000 {
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020c0000 0x4000>;
|
|
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clks: ccm@020c4000 {
|
|
compatible = "fsl,imx6q-ccm";
|
|
reg = <0x020c4000 0x4000>;
|
|
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
anatop: anatop@020c8000 {
|
|
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
|
|
reg = <0x020c8000 0x1000>;
|
|
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
regulator-1p1 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd1p1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1375000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x110>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <4>;
|
|
anatop-min-voltage = <800000>;
|
|
anatop-max-voltage = <1375000>;
|
|
};
|
|
|
|
regulator-3p0 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd3p0";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <3150000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x120>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2625000>;
|
|
anatop-max-voltage = <3400000>;
|
|
};
|
|
|
|
regulator-2p5 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd2p5";
|
|
regulator-min-microvolt = <2000000>;
|
|
regulator-max-microvolt = <2750000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x130>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2000000>;
|
|
anatop-max-voltage = <2750000>;
|
|
};
|
|
|
|
reg_arm: regulator-vddcore {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddarm";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <0>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <24>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_pu: regulator-vddpu {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-enable-ramp-delay = <150>;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <9>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <26>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_soc: regulator-vddsoc {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddsoc";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <18>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <28>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
};
|
|
|
|
tempmon: tempmon {
|
|
compatible = "fsl,imx6q-tempmon";
|
|
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,tempmon = <&anatop>;
|
|
fsl,tempmon-data = <&ocotp>;
|
|
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
|
};
|
|
|
|
usbphy1: usbphy@020c9000 {
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020c9000 0x1000>;
|
|
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
usbphy2: usbphy@020ca000 {
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020ca000 0x1000>;
|
|
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBPHY2>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
snvs: snvs@020cc000 {
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
reg = <0x020cc000 0x4000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap = <&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
snvs_poweroff: snvs-poweroff {
|
|
compatible = "syscon-poweroff";
|
|
regmap = <&snvs>;
|
|
offset = <0x38>;
|
|
mask = <0x60>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epit1: epit@020d0000 { /* EPIT1 */
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
epit2: epit@020d4000 { /* EPIT2 */
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
src: src@020d8000 {
|
|
compatible = "fsl,imx6q-src", "fsl,imx51-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@020dc000 {
|
|
compatible = "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&intc>;
|
|
pu-supply = <®_pu>;
|
|
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
|
|
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
|
|
<&clks IMX6QDL_CLK_GPU2D_CORE>,
|
|
<&clks IMX6QDL_CLK_GPU2D_AXI>,
|
|
<&clks IMX6QDL_CLK_OPENVG_AXI>,
|
|
<&clks IMX6QDL_CLK_VPU_AXI>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@020e0000 {
|
|
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
|
|
reg = <0x020e0000 0x38>;
|
|
};
|
|
|
|
iomuxc: iomuxc@020e0000 {
|
|
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
};
|
|
|
|
ldb: ldb@020e0008 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
|
|
gpr = <&gpr>;
|
|
status = "disabled";
|
|
|
|
lvds-channel@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
status = "disabled";
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
lvds0_mux_0: endpoint {
|
|
remote-endpoint = <&ipu1_di0_lvds0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
lvds0_mux_1: endpoint {
|
|
remote-endpoint = <&ipu1_di1_lvds0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds-channel@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
status = "disabled";
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
lvds1_mux_0: endpoint {
|
|
remote-endpoint = <&ipu1_di0_lvds1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
lvds1_mux_1: endpoint {
|
|
remote-endpoint = <&ipu1_di1_lvds1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dcic1: dcic@020e4000 {
|
|
reg = <0x020e4000 0x4000>;
|
|
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dcic2: dcic@020e8000 {
|
|
reg = <0x020e8000 0x4000>;
|
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sdma: sdma@020ec000 {
|
|
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
|
reg = <0x020ec000 0x4000>;
|
|
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_SDMA>,
|
|
<&clks IMX6QDL_CLK_SDMA>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
|
};
|
|
};
|
|
|
|
aips-bus@02100000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
crypto: caam@2100000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
fsl,sec-era = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x2100000 0x10000>;
|
|
ranges = <0 0x2100000 0x10000>;
|
|
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
|
|
<&clks IMX6QDL_CLK_CAAM_ACLK>,
|
|
<&clks IMX6QDL_CLK_CAAM_IPG>,
|
|
<&clks IMX6QDL_CLK_EIM_SLOW>;
|
|
clock-names = "mem", "aclk", "ipg", "emi_slow";
|
|
|
|
sec_jr0: jr0@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr1@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
aipstz@0217c000 { /* AIPSTZ2 */
|
|
reg = <0x0217c000 0x4000>;
|
|
};
|
|
|
|
usbotg: usb@02184000 {
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@02184200 {
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
dr_mode = "host";
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@02184400 {
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184400 0x200>;
|
|
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
dr_mode = "host";
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh3: usb@02184600 {
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184600 0x200>;
|
|
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
|
fsl,usbmisc = <&usbmisc 3>;
|
|
dr_mode = "host";
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@02184800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx6q-usbmisc";
|
|
reg = <0x02184800 0x200>;
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
|
};
|
|
|
|
fec: ethernet@02188000 {
|
|
compatible = "fsl,imx6q-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupts-extended =
|
|
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_ENET>,
|
|
<&clks IMX6QDL_CLK_ENET>,
|
|
<&clks IMX6QDL_CLK_ENET_REF>;
|
|
clock-names = "ipg", "ahb", "ptp";
|
|
status = "disabled";
|
|
};
|
|
|
|
mlb@0218c000 {
|
|
reg = <0x0218c000 0x4000>;
|
|
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
usdhc1: usdhc@02190000 {
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USDHC1>,
|
|
<&clks IMX6QDL_CLK_USDHC1>,
|
|
<&clks IMX6QDL_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@02194000 {
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USDHC2>,
|
|
<&clks IMX6QDL_CLK_USDHC2>,
|
|
<&clks IMX6QDL_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: usdhc@02198000 {
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USDHC3>,
|
|
<&clks IMX6QDL_CLK_USDHC3>,
|
|
<&clks IMX6QDL_CLK_USDHC3>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc4: usdhc@0219c000 {
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x0219c000 0x4000>;
|
|
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_USDHC4>,
|
|
<&clks IMX6QDL_CLK_USDHC4>,
|
|
<&clks IMX6QDL_CLK_USDHC4>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@021a0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@021a4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@021a8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
romcp@021ac000 {
|
|
reg = <0x021ac000 0x4000>;
|
|
};
|
|
|
|
mmdc0: mmdc@021b0000 { /* MMDC0 */
|
|
compatible = "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
};
|
|
|
|
mmdc1: mmdc@021b4000 { /* MMDC1 */
|
|
reg = <0x021b4000 0x4000>;
|
|
};
|
|
|
|
weim: weim@021b8000 {
|
|
compatible = "fsl,imx6q-weim";
|
|
reg = <0x021b8000 0x4000>;
|
|
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
|
|
};
|
|
|
|
ocotp: ocotp@021bc000 {
|
|
compatible = "fsl,imx6q-ocotp", "syscon";
|
|
reg = <0x021bc000 0x4000>;
|
|
clocks = <&clks IMX6QDL_CLK_IIM>;
|
|
};
|
|
|
|
tzasc@021d0000 { /* TZASC1 */
|
|
reg = <0x021d0000 0x4000>;
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
tzasc@021d4000 { /* TZASC2 */
|
|
reg = <0x021d4000 0x4000>;
|
|
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
audmux: audmux@021d8000 {
|
|
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
|
|
reg = <0x021d8000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi_csi: mipi@021dc000 {
|
|
reg = <0x021dc000 0x4000>;
|
|
};
|
|
|
|
mipi_dsi: mipi@021e0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x021e0000 0x4000>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mipi_mux_0: endpoint {
|
|
remote-endpoint = <&ipu1_di0_mipi>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mipi_mux_1: endpoint {
|
|
remote-endpoint = <&ipu1_di1_mipi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vdoa@021e4000 {
|
|
reg = <0x021e4000 0x4000>;
|
|
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
uart2: serial@021e8000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021e8000 0x4000>;
|
|
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@021ec000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021ec000 0x4000>;
|
|
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@021f0000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021f0000 0x4000>;
|
|
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@021f4000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021f4000 0x4000>;
|
|
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ipu1: ipu@02400000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ipu";
|
|
reg = <0x02400000 0x400000>;
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6QDL_CLK_IPU1>,
|
|
<&clks IMX6QDL_CLK_IPU1_DI0>,
|
|
<&clks IMX6QDL_CLK_IPU1_DI1>;
|
|
clock-names = "bus", "di0", "di1";
|
|
resets = <&src 2>;
|
|
|
|
ipu1_csi0: port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
ipu1_csi1: port@1 {
|
|
reg = <1>;
|
|
};
|
|
|
|
ipu1_di0: port@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
|
|
ipu1_di0_disp0: disp0-endpoint {
|
|
};
|
|
|
|
ipu1_di0_hdmi: hdmi-endpoint {
|
|
remote-endpoint = <&hdmi_mux_0>;
|
|
};
|
|
|
|
ipu1_di0_mipi: mipi-endpoint {
|
|
remote-endpoint = <&mipi_mux_0>;
|
|
};
|
|
|
|
ipu1_di0_lvds0: lvds0-endpoint {
|
|
remote-endpoint = <&lvds0_mux_0>;
|
|
};
|
|
|
|
ipu1_di0_lvds1: lvds1-endpoint {
|
|
remote-endpoint = <&lvds1_mux_0>;
|
|
};
|
|
};
|
|
|
|
ipu1_di1: port@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
|
|
ipu1_di1_disp1: disp1-endpoint {
|
|
};
|
|
|
|
ipu1_di1_hdmi: hdmi-endpoint {
|
|
remote-endpoint = <&hdmi_mux_1>;
|
|
};
|
|
|
|
ipu1_di1_mipi: mipi-endpoint {
|
|
remote-endpoint = <&mipi_mux_1>;
|
|
};
|
|
|
|
ipu1_di1_lvds0: lvds0-endpoint {
|
|
remote-endpoint = <&lvds0_mux_1>;
|
|
};
|
|
|
|
ipu1_di1_lvds1: lvds1-endpoint {
|
|
remote-endpoint = <&lvds1_mux_1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|