forked from Minki/linux
00e729c933
These are as usual a very large number of mostly boring updates to enable devices in existing machines, or to fix minor bugs. Notably, an ongoing treewide effort to fix warnings caused by an update to the device tree compiler. These are enabled with "make W=1" at the moment but can hopefully become the default once all issues have been addressed. No new SoC platform is added this time around (Armada 395 and Orion mv88f5181 are slight variations of existing ones), but a significant number of new dts files are added, which I list by platform: - Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets; Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E, Orange Pi Lite, Olimex A33-Olinuxino, and Nano Pi Neo single-board computers - ARM Realview: all supported machines (ported from board files) - Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and BCM958622hr reference boards for Northstar platform; Raspberry Pi Zero single-board computer - Marvell EBU: Netgear WNR854T router (ported from board file); Armada 395 SoC platform and GP board Armada 390 DB development board - NXP i.MX: imx7s Warp7 reference board; Gateworks Ventana GW553x single-board computer, Technologic Systems TS-4900 and Engicam IMX6UL GEA M6UL computer-on-module, Inverse Path USB armory board - Qualcomm: LG Nexus 5 Phone - Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards - Rockchip: Rockchip RK3288 Fennec reference board; Firefly RK3288 Reload platform - ST Microelectronics STi: B2260 (96boards) single-board computer - TI Davinci: OMAP-L138 LCDK Development kit - TI OMAP: beagleboard-x15 rev B1 single-board computer Conflicts: vendor-prefixes.txt has conflicting additions, keep all of them in alphabetical order. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAV/g11mCrR//JCVInAQIWbw/9FOrBghI2bFqZkDwFE8E3QCpc9bIiETMx FMdHV6FAo0D6Yp4EqlWjFI0u0Kn9l4FKz0SYWAigpfT6gfeI1THC2Kl31mslvb5U v3QreXI4rKjZS/B1lYECee0os+fNvJcWKj3uFjb4VT1k7T6+MytjHGAQSzwxM66Q 0Lp5HjdFGDrOXoIUx2eEZkZlVXyQ2EFocMoAsj+s/MHnA8fn1tWW08633kjTsC6y 9Xj71joghlDKZjA56htaEQ+/6dYdxAHVlvkN7aL9di+2Sc2/ma6my70Zvs4zwtOv uJDhcJhjwvf3QtDuOoGhTnFtQYQWaONaGUFyEwYyy2kIwiJy0afep4JCq2o+/CZM VMvGXepJpVujE9mg+LwHPgaMYgBhswsJzwQ2ZESrMQcUZ624E18dG2/ei5zat4UN 5/NvzxEoDGmfQFQUpuoZuPqhwLRauXr7I+u4aliIdtSBGeaA2T1yFT4pVgNUOxBQ 0bMtE2QSUKyaF+xAHLTsV7yheDU0S+C7zVkLPwePK0V7vUFuBsdQiXEqXh/6MSq0 iYVPmKwNTIHK3qMiGtm8XDugjR8Pf0tCXRqIWJMlXs75rCAsKfFW4j4XYnlO4wMy dP2fdoe0xA+zthR0hRHD5i8WCmISeUgtPAdFyTid1jZkMk1AzM0AqBUdAqTInvQ3 O4JSYcjBWoo= =/gg/ -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "These are as usual a very large number of mostly boring updates to enable devices in existing machines, or to fix minor bugs. Notably, an ongoing treewide effort to fix warnings caused by an update to the device tree compiler. These are enabled with "make W=1" at the moment but can hopefully become the default once all issues have been addressed. No new SoC platform is added this time around (Armada 395 and Orion mv88f5181 are slight variations of existing ones), but a significant number of new dts files are added, which I list by platform: - Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets, Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E, Orange Pi Lite, Olimex A33-Olinuxino, and Nano Pi Neo single-board computers - ARM Realview: all supported machines (ported from board files) - Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and BCM958622hr reference boards for Northstar platform, Raspberry Pi Zero single-board computer - Marvell EBU: Netgear WNR854T router (ported from board file), Armada 395 SoC platform and GP board Armada 390 DB development board - NXP i.MX: imx7s Warp7 reference board, Gateworks Ventana GW553x single-board computer, Technologic Systems TS-4900 and Engicam IMX6UL GEA M6UL computer-on-module, Inverse Path USB armory board - Qualcomm: LG Nexus 5 Phone - Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards - Rockchip: Rockchip RK3288 Fennec reference board, Firefly RK3288 Reload platform - ST Microelectronics STi: B2260 (96boards) single-board computer - TI Davinci: OMAP-L138 LCDK Development kit - TI OMAP: beagleboard-x15 rev B1 single-board computer" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (390 commits) ARM: dts: sony-nsz-gs7: add missing unit name to /memory node ARM: dts: chromecast: add missing unit name to /memory node ARM: dts: berlin2q-marvell-dmp: add missing unit name to /memory node ARM: dts: berlin2: Add missing unit name to /soc node ARM: dts: berlin2cd: Add missing unit name to /soc node ARM: dts: berlin2q: Add missing unit name to /soc node ARM: dts: berlin2: Remove skeleton.dtsi inclusion ARM: dts: berlin2cd: Remove skeleton.dtsi inclusion ARM: dts: berlin2q: Remove skeleton.dtsi inclusion arm: dts: berlin2q: enable all wdt nodes unconditionally arm: dts: berlin2: enable all wdt nodes unconditionally ARM: dts: omap5-igep0050.dts: Use tabs for indentation ARM: dts: Fix igepv5 power button GPIO direction ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node ARM: dts: s3c64xx: Use macros for pinctrl configuration ARM: dts: s3c2416: Use macros for pinctrl configuration ARM: dts: s5pv210: Use macros for pinctrl configuration ARM: dts: s3c64xx: Use common macros for pinctrl configuration ...
447 lines
10 KiB
Plaintext
447 lines
10 KiB
Plaintext
/*
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* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "armada-388.dtsi"
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#include "armada-38x-solidrun-microsom.dtsi"
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/ {
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model = "SolidRun Clearfog A1";
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compatible = "solidrun,clearfog-a1", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet1 = ð0;
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ethernet2 = ð1;
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ethernet3 = ð2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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soc {
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internal-regs {
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ethernet@30000 {
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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bm,pool-short = <1>;
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet@34000 {
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <3>;
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bm,pool-short = <1>;
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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i2c@11000 {
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/* Is there anything on this? */
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* PCA9655 GPIO expander, up to 1MHz clock.
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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expander0: gpio-expander@20 {
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/*
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* This is how it should be:
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* compatible = "onnn,pca9655",
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* "nxp,pca9555";
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* but you can't do this because of
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* the way I2C works.
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*/
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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pcie1_0_clkreq {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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pcie1_0_w_disable {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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usb3_ilimit {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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input;
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line-name = "usb3-current-limit";
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};
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usb3_power {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb3-power";
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};
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m2_devslp {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "m.2 devslp";
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};
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sfp_los {
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/* SFP loss of signal */
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_HIGH>;
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input;
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line-name = "sfp-los";
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};
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sfp_tx_fault {
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/* SFP laser fault */
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gpio-hog;
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gpios = <13 GPIO_ACTIVE_HIGH>;
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input;
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line-name = "sfp-tx-fault";
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};
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sfp_tx_disable {
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/* SFP transmit disable */
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gpio-hog;
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gpios = <14 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "sfp-tx-disable";
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};
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sfp_mod_def0 {
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/* SFP module present */
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_LOW>;
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input;
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line-name = "sfp-mod-def0";
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};
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};
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/* The MCP3021 is 100kHz clock only */
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mikrobus_adc: mcp3021@4c {
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compatible = "microchip,mcp3021";
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reg = <0x4c>;
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};
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/* Also something at 0x64 */
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};
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i2c@11100 {
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/*
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* Routed to SFP, mikrobus, and PCIe.
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* SFP limits this to 100kHz, and requires
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* an AT24C01A/02/04 with address pins tied
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* low, which takes addresses 0x50 and 0x51.
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* Mikrobus doesn't specify beyond an I2C
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* bus being present.
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* PCIe uses ARP to assign addresses, or
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* 0x63-0x64.
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*/
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clock-frequency = <100000>;
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pinctrl-0 = <&clearfog_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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pinctrl@18000 {
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clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
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marvell,pins = "mpp46";
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marvell,function = "ref";
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};
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clearfog_dsa0_pins: clearfog-dsa0-pins {
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marvell,pins = "mpp23", "mpp41";
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marvell,function = "gpio";
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};
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clearfog_i2c1_pins: i2c1-pins {
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/* SFP, PCIe, mSATA, mikrobus */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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clearfog_sdhci_pins: clearfog-sdhci-pins {
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marvell,pins = "mpp21", "mpp28",
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"mpp37", "mpp38",
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"mpp39", "mpp40";
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marvell,function = "sd0";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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mikro_pins: mikro-pins {
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/* int: mpp22 rst: mpp29 */
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marvell,pins = "mpp22", "mpp29";
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marvell,function = "gpio";
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};
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mikro_spi_pins: mikro-spi-pins {
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marvell,pins = "mpp43";
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marvell,function = "spi1";
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};
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mikro_uart_pins: mikro-uart-pins {
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marvell,pins = "mpp24", "mpp25";
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marvell,function = "ua1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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sata@a8000 {
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/* pinctrl? */
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status = "okay";
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};
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sata@e0000 {
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/* pinctrl? */
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status = "okay";
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};
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sdhci@d8000 {
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bus-width = <4>;
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cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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pinctrl-0 = <&clearfog_sdhci_pins
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&clearfog_sdhci_cd_pins>;
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pinctrl-names = "default";
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status = "okay";
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vmmc = <®_3p3v>;
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wp-inverted;
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};
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serial@12100 {
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/* mikrobus uart */
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pinctrl-0 = <&mikro_uart_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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usb@58000 {
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/* CON3, nearest power. */
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status = "okay";
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};
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usb3@f0000 {
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/* CON2, nearest CPU, USB2 only. */
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status = "okay";
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};
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usb3@f8000 {
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/* CON7 */
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* the mini-PCIe connectors on the board.
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*/
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pcie@2,0 {
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/* Port 1, Lane 0. CON3, nearest power. */
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reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0. CON2, nearest CPU. */
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reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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};
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dsa@0 {
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compatible = "marvell,dsa";
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dsa,ethernet = <ð1>;
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dsa,mii-bus = <&mdio>;
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
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pinctrl-names = "default";
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#address-cells = <2>;
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#size-cells = <0>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4 0>;
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port@0 {
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reg = <0>;
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label = "lan5";
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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port@6 {
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/* 88E1512 external phy */
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reg = <6>;
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label = "lan6";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
|
linux,can-disable;
|
|
linux,code = <BTN_0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi1 {
|
|
/*
|
|
* We don't seem to have the W25Q32 on the
|
|
* A1 Rev 2.0 boards, so disable SPI.
|
|
* CS0: W25Q32 (doesn't appear to be present)
|
|
* CS1:
|
|
* CS2: mikrobus
|
|
*/
|
|
pinctrl-0 = <&spi1_pins
|
|
&clearfog_spi1_cs_pins
|
|
&mikro_spi_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
spi-flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "w25q32", "jedec,spi-nor";
|
|
reg = <0>; /* Chip select 0 */
|
|
spi-max-frequency = <3000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|