forked from Minki/linux
042000b003
Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.
$cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc1 2 2 25000000
sdram_pll 0 0 400000000
s2f_usr2_clk 0 0 66666666
ddr_dq_clk 0 0 200000000
ddr_2x_dqs_clk 0 0 400000000
ddr_dqs_clk 0 0 200000000
periph_pll 2 2 500000000
s2f_usr1_clk 0 0 50000000
per_base_clk 4 4 100000000
per_nand_mmc_clk 0 0 25000000
per_qsi_clk 0 0 250000000
emac1_clk 1 1 125000000
emac0_clk 0 0 125000000
main_pll 1 1 1600000000
cfg_s2f_usr0_clk 0 0 100000000
main_nand_sdmmc_clk 0 0 100000000
main_qspi_clk 0 0 400000000
dbg_base_clk 0 0 400000000
mainclk 0 0 400000000
mpuclk 1 1 800000000
smp_twd 1 1 200000000
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
73 lines
1.5 KiB
Plaintext
73 lines
1.5 KiB
Plaintext
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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/ {
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model = "Altera SOCFPGA Cyclone V";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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