forked from Minki/linux
03d576f202
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. As this can not be guaranteed by the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. A workaround to set the muxes once during boot could be added to the kernel or bootloader. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
207 lines
6.4 KiB
C
207 lines
6.4 KiB
C
#ifndef __MACH_IMX_CLK_H
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#define __MACH_IMX_CLK_H
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#include <linux/spinlock.h>
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#include <linux/clk-provider.h>
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extern spinlock_t imx_ccm_lock;
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void imx_check_clocks(struct clk *clks[], unsigned int count);
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void imx_register_uart_clocks(struct clk ** const clks[]);
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extern void imx_cscmr1_fixup(u32 *val);
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enum imx_pllv1_type {
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IMX_PLLV1_IMX1,
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IMX_PLLV1_IMX21,
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IMX_PLLV1_IMX25,
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IMX_PLLV1_IMX27,
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IMX_PLLV1_IMX31,
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IMX_PLLV1_IMX35,
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};
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struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
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const char *parent, void __iomem *base);
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_USB_VF610,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_ENET_IMX7,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate_flags, spinlock_t *lock,
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unsigned int *share_count);
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struct clk * imx_obtain_fixed_clock(
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const char *name, unsigned long rate);
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struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u32 exclusive_mask);
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width,
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void __iomem *busy_reg, u8 busy_shift);
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struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
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u8 width, void __iomem *busy_reg, u8 busy_shift,
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const char **parent_names, int num_parents);
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struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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void (*fixup)(u32 *val));
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struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents,
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int num_parents, void (*fixup)(u32 *val));
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static inline struct clk *imx_clk_fixed(const char *name, int rate)
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{
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return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
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shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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unsigned long flags)
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{
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return clk_register_divider(NULL, name, parent, flags,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate2_shared(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_shared2(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
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&imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_cgr(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, cgr_val, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux_flags(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **parents,
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int num_parents, unsigned long flags)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
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&imx_ccm_lock);
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}
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struct clk *imx_clk_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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#endif
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