linux/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
Marek Vasut 5b5ada57e4 ARM: dts: socfpga: Add second ethernet alias to VINING FPGA
Add DT alias for the second ethernet present on mainboard rev 1.10.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23 09:29:12 -05:00

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/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "samtec VIN|ING FPGA";
compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
/*
* This allow the ethaddr uboot environment variable contents
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
ethernet1 = &gmac0;
};
gpio-keys {
compatible = "gpio-keys";
hps_temp0 {
label = "BTN_0"; /* TEMP_OS */
gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
linux,code = <BTN_0>;
};
hps_hkey0 {
label = "BTN_1"; /* DIS_PWR */
gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
linux,code = <BTN_1>;
};
hps_hkey1 {
label = "hps_hkey1"; /* POWER_DOWN */
gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
linux,code = <KEY_POWER>;
};
};
regulator-usb-nrst {
compatible = "regulator-fixed";
regulator-name = "usb_nrst";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy1>;
snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <10000 10000 10000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <1>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
};
};
&gpio0 { /* GPIO 0..29 */
status = "okay";
};
&gpio1 { /* GPIO 30..57 */
status = "okay";
};
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
&i2c0 {
status = "okay";
gpio: pca9557@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
gpio-controller;
#gpio-cells = <2>;
};
temp: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
at24@50 {
compatible = "at24,24c01";
pagesize = <8>;
reg = <0x50>;
};
i2cswitch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { /* Backplane EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
eeprom@51 {
compatible = "at,24c01";
pagesize = <8>;
reg = <0x51>;
};
};
i2c@7 { /* Power board EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
eeprom@51 {
compatible = "at,24c01";
pagesize = <8>;
reg = <0x51>;
};
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
at24@50 {
compatible = "at24,24c02";
pagesize = <8>;
reg = <0x50>;
};
};
&qspi {
status = "okay";
n25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
n25q00@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
reg = <1>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
&usb0 {
dr_mode = "host";
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};