forked from Minki/linux
035cd485a4
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term frequency drift. The frequency drift magnitude depends on the VCO update rate, which is inversely proportional to the PLL divider. The kernel DPLL configuration code results in a high value for the divider, leading to a long term drift high enough to cause USB transmission errors. In the worst case the USB PHY's ULPI interface can stop responding, breaking USB operation completely. This manifests itself on the Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the cable is bad?' in the kernel log. Errata sprz319 advisory 2.1 documents PLL values that minimize the drift. Use them automatically when DPLL5 is used for USB operation, which we detect based on the requested clock rate. The clock framework will still compute the PLL parameters and resulting rate as usual, but the PLL M and N values will then be overridden. This can result in the effective clock rate being slightly different than the rate cached by the clock framework, but won't cause any adverse effect to USB operation. Signed-off-by: Richard Watts <rrw@kynesim.co.uk> [Upported from v3.2 to v4.9] Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| adpll.c | ||
| apll.c | ||
| autoidle.c | ||
| clk-2xxx.c | ||
| clk-3xxx-legacy.c | ||
| clk-3xxx.c | ||
| clk-7xx.c | ||
| clk-33xx.c | ||
| clk-43xx.c | ||
| clk-44xx.c | ||
| clk-54xx.c | ||
| clk-814x.c | ||
| clk-816x.c | ||
| clk-dra7-atl.c | ||
| clk.c | ||
| clkt_dflt.c | ||
| clkt_dpll.c | ||
| clkt_iclk.c | ||
| clock.h | ||
| clockdomain.c | ||
| composite.c | ||
| divider.c | ||
| dpll3xxx.c | ||
| dpll44xx.c | ||
| dpll.c | ||
| fapll.c | ||
| fixed-factor.c | ||
| gate.c | ||
| interface.c | ||
| Kconfig | ||
| Makefile | ||
| mux.c | ||