forked from Minki/linux
09cb2e3667
Update the STI timer frequency comment to 32.768 kHz to fix 37 kHz typo. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
250 lines
6.5 KiB
C
250 lines
6.5 KiB
C
/*
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* Emma Mobile EV2 clock framework support
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*
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* Copyright (C) 2012 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#define EMEV2_SMU_BASE 0xe0110000
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/* EMEV2 SMU registers */
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#define USIAU0_RSTCTRL 0x094
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#define USIBU1_RSTCTRL 0x0ac
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#define USIBU2_RSTCTRL 0x0b0
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#define USIBU3_RSTCTRL 0x0b4
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#define STI_RSTCTRL 0x124
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#define USIAU0GCLKCTRL 0x4a0
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#define USIBU1GCLKCTRL 0x4b8
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#define USIBU2GCLKCTRL 0x4bc
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#define USIBU3GCLKCTRL 0x04c0
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#define STIGCLKCTRL 0x528
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#define USIAU0SCLKDIV 0x61c
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#define USIB2SCLKDIV 0x65c
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#define USIB3SCLKDIV 0x660
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#define STI_CLKSEL 0x688
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#define SMU_GENERAL_REG0 0x7c0
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/* not pretty, but hey */
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static void __iomem *smu_base;
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static void emev2_smu_write(unsigned long value, int offs)
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{
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BUG_ON(!smu_base || (offs >= PAGE_SIZE));
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iowrite32(value, smu_base + offs);
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}
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void emev2_set_boot_vector(unsigned long value)
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{
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emev2_smu_write(value, SMU_GENERAL_REG0);
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}
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static struct clk_mapping smu_mapping = {
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.phys = EMEV2_SMU_BASE,
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.len = PAGE_SIZE,
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};
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/* Fixed 32 KHz root clock from C32K pin */
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static struct clk c32k_clk = {
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.rate = 32768,
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.mapping = &smu_mapping,
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};
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/* PLL3 multiplies C32K with 7000 */
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static unsigned long pll3_recalc(struct clk *clk)
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{
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return clk->parent->rate * 7000;
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}
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static struct sh_clk_ops pll3_clk_ops = {
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.recalc = pll3_recalc,
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};
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static struct clk pll3_clk = {
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.ops = &pll3_clk_ops,
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.parent = &c32k_clk,
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};
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static struct clk *main_clks[] = {
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&c32k_clk,
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&pll3_clk,
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};
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enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3,
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SCLKDIV_NR };
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#define SCLKDIV(_reg, _shift) \
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{ \
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.parent = &pll3_clk, \
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.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
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.enable_bit = _shift, \
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}
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static struct clk sclkdiv_clks[SCLKDIV_NR] = {
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[SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0),
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[SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16),
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[SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0),
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[SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0),
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};
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enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
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GCLK_STI_SCLK,
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GCLK_NR };
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#define GCLK_SCLK(_parent, _reg) \
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{ \
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.parent = _parent, \
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.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
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.enable_bit = 1, /* SCLK_GCC */ \
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}
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static struct clk gclk_clks[GCLK_NR] = {
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[GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0],
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USIAU0GCLKCTRL),
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[GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1],
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USIBU1GCLKCTRL),
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[GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2],
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USIBU2GCLKCTRL),
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[GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
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USIBU3GCLKCTRL),
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[GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
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};
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static int emev2_gclk_enable(struct clk *clk)
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{
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iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
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clk->mapped_reg);
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return 0;
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}
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static void emev2_gclk_disable(struct clk *clk)
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{
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iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
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clk->mapped_reg);
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}
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static struct sh_clk_ops emev2_gclk_clk_ops = {
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.enable = emev2_gclk_enable,
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.disable = emev2_gclk_disable,
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.recalc = followparent_recalc,
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};
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static int __init emev2_gclk_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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int ret = 0;
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int k;
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &emev2_gclk_clk_ops;
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ret |= clk_register(clkp);
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}
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return ret;
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}
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static unsigned long emev2_sclkdiv_recalc(struct clk *clk)
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{
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unsigned int sclk_div;
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sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff;
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return clk->parent->rate / (sclk_div + 1);
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}
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static struct sh_clk_ops emev2_sclkdiv_clk_ops = {
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.recalc = emev2_sclkdiv_recalc,
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};
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static int __init emev2_sclkdiv_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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int ret = 0;
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int k;
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &emev2_sclkdiv_clk_ops;
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ret |= clk_register(clkp);
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}
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return ret;
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}
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static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]),
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CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]),
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CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]),
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CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]),
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CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]),
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CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]),
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CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]),
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CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
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CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
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CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
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};
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void __init emev2_clock_init(void)
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{
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int k, ret = 0;
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static int is_setup;
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/* yuck, this is ugly as hell, but the non-smp case of clocks
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* code is now designed to rely on ioremap() instead of static
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* entity maps. in the case of smp we need access to the SMU
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* register earlier than ioremap() is actually working without
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* any static maps. to enable SMP in ugly but with dynamic
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* mappings we have to call emev2_clock_init() from different
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* places depending on UP and SMP...
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*/
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if (is_setup++)
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return;
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smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
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BUG_ON(!smu_base);
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/* setup STI timer to run on 32.768 kHz and deassert reset */
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emev2_smu_write(0, STI_CLKSEL);
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emev2_smu_write(1, STI_RSTCTRL);
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/* deassert reset for UART0->UART3 */
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emev2_smu_write(2, USIAU0_RSTCTRL);
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emev2_smu_write(2, USIBU1_RSTCTRL);
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emev2_smu_write(2, USIBU2_RSTCTRL);
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emev2_smu_write(2, USIBU3_RSTCTRL);
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR);
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if (!ret)
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ret = emev2_gclk_register(gclk_clks, GCLK_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup emev2 clocks\n");
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}
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