Hai Li b96b3a06d1 drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH ... This change takes advantage of a HW feature that synchronize flush operation on CTL1 to CTL0, to keep dual DSI pipes in sync. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2015-08-15 18:27:16 -04:00
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mdp4	drm/msm: don't install plane properties on crtc	2015-08-15 18:27:15 -04:00
mdp5	drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH	2015-08-15 18:27:16 -04:00
mdp_common.xml.h	drm/msm: update generated headers	2015-08-15 18:27:10 -04:00
mdp_format.c	drm/msm: update generated headers	2015-08-15 18:27:10 -04:00
mdp_kms.c	drm/msm: Do not BUG_ON(!spin_is_locked()) on UP	2015-02-01 15:30:25 -05:00
mdp_kms.h	drm/msm: update generated headers	2015-08-15 18:27:10 -04:00