02ab1f5018
Errata 1165522, 1319367 and 1530923 each allow TLB entries to be allocated as a result of a speculative AT instruction. In order to avoid mandating VHE on certain affected CPUs, apply the workaround to both the nVHE and the VHE case for all affected CPUs. Signed-off-by: Andrew Scull <ascull@google.com> Acked-by: Will Deacon <will@kernel.org> CC: Marc Zyngier <maz@kernel.org> CC: James Morse <james.morse@arm.com> CC: Suzuki K Poulose <suzuki.poulose@arm.com> CC: Will Deacon <will@kernel.org> CC: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20200504094858.108917-1-ascull@google.com Signed-off-by: Will Deacon <will@kernel.org>
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm64/include/asm/cpucaps.h
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*
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* Copyright (C) 2016 ARM Ltd.
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*/
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#ifndef __ASM_CPUCAPS_H
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#define __ASM_CPUCAPS_H
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#define ARM64_WORKAROUND_CLEAN_CACHE 0
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#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
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#define ARM64_WORKAROUND_845719 2
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#define ARM64_HAS_SYSREG_GIC_CPUIF 3
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#define ARM64_HAS_PAN 4
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#define ARM64_HAS_LSE_ATOMICS 5
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#define ARM64_WORKAROUND_CAVIUM_23154 6
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#define ARM64_WORKAROUND_834220 7
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#define ARM64_HAS_NO_HW_PREFETCH 8
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#define ARM64_HAS_UAO 9
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#define ARM64_ALT_PAN_NOT_UAO 10
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#define ARM64_HAS_VIRT_HOST_EXTN 11
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#define ARM64_WORKAROUND_CAVIUM_27456 12
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#define ARM64_HAS_32BIT_EL0 13
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#define ARM64_HARDEN_EL2_VECTORS 14
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#define ARM64_HAS_CNP 15
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#define ARM64_HAS_NO_FPSIMD 16
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#define ARM64_WORKAROUND_REPEAT_TLBI 17
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#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
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#define ARM64_WORKAROUND_858921 19
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#define ARM64_WORKAROUND_CAVIUM_30115 20
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#define ARM64_HAS_DCPOP 21
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#define ARM64_SVE 22
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HAS_RAS_EXTN 25
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#define ARM64_WORKAROUND_843419 26
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#define ARM64_HAS_CACHE_IDC 27
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#define ARM64_HAS_CACHE_DIC 28
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#define ARM64_HW_DBM 29
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#define ARM64_SSBD 30
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#define ARM64_MISMATCHED_CACHE_TYPE 31
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#define ARM64_HAS_STAGE2_FWB 32
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#define ARM64_HAS_CRC32 33
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#define ARM64_SSBS 34
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#define ARM64_WORKAROUND_1418040 35
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#define ARM64_HAS_SB 36
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#define ARM64_WORKAROUND_SPECULATIVE_AT 37
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#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
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#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
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#define ARM64_HAS_GENERIC_AUTH_ARCH 40
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#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
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#define ARM64_HAS_IRQ_PRIO_MASKING 42
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#define ARM64_HAS_DCPODP 43
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#define ARM64_WORKAROUND_1463225 44
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_HAS_E0PD 48
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#define ARM64_HAS_RNG 49
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#define ARM64_HAS_AMU_EXTN 50
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#define ARM64_HAS_ADDRESS_AUTH 51
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#define ARM64_HAS_GENERIC_AUTH 52
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#define ARM64_NCAPS 53
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#endif /* __ASM_CPUCAPS_H */
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