forked from Minki/linux
007bb689b3
The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
/*
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* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
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#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
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/* MPUMODRST */
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#define CPU0_RESET 0
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#define CPU1_RESET 1
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#define WDS_RESET 2
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#define SCUPER_RESET 3
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/* PER0MODRST */
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#define EMAC0_RESET 32
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#define EMAC1_RESET 33
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#define EMAC2_RESET 34
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#define USB0_RESET 35
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#define USB1_RESET 36
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#define NAND_RESET 37
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#define QSPI_RESET 38
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#define SDMMC_RESET 39
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#define EMAC0_OCP_RESET 40
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#define EMAC1_OCP_RESET 41
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#define EMAC2_OCP_RESET 42
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#define USB0_OCP_RESET 43
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#define USB1_OCP_RESET 44
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#define NAND_OCP_RESET 45
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#define QSPI_OCP_RESET 46
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#define SDMMC_OCP_RESET 47
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#define DMA_RESET 48
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#define SPIM0_RESET 49
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#define SPIM1_RESET 50
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#define SPIS0_RESET 51
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#define SPIS1_RESET 52
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#define DMA_OCP_RESET 53
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#define EMAC_PTP_RESET 54
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/* 55 is empty*/
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#define DMAIF0_RESET 56
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#define DMAIF1_RESET 57
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#define DMAIF2_RESET 58
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#define DMAIF3_RESET 59
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#define DMAIF4_RESET 60
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#define DMAIF5_RESET 61
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#define DMAIF6_RESET 62
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#define DMAIF7_RESET 63
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/* PER1MODRST */
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#define L4WD0_RESET 64
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#define L4WD1_RESET 65
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#define L4SYSTIMER0_RESET 66
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#define L4SYSTIMER1_RESET 67
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#define SPTIMER0_RESET 68
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#define SPTIMER1_RESET 69
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/* 70-71 is reserved */
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#define I2C0_RESET 72
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#define I2C1_RESET 73
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#define I2C2_RESET 74
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#define I2C3_RESET 75
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#define I2C4_RESET 76
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/* 77-79 is reserved */
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#define UART0_RESET 80
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#define UART1_RESET 81
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/* 82-87 is reserved */
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#define GPIO0_RESET 88
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#define GPIO1_RESET 89
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#define GPIO2_RESET 90
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/* BRGMODRST */
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#define HPS2FPGA_RESET 96
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#define LWHPS2FPGA_RESET 97
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#define FPGA2HPS_RESET 98
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#define F2SSDRAM0_RESET 99
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#define F2SSDRAM1_RESET 100
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#define F2SSDRAM2_RESET 101
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#define DDRSCH_RESET 102
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/* SYSMODRST*/
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#define ROM_RESET 128
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#define OCRAM_RESET 129
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/* 130 is reserved */
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#define FPGAMGR_RESET 131
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#define S2F_RESET 132
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#define SYSDBG_RESET 133
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#define OCRAM_OCP_RESET 134
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/* COLDMODRST */
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#define CLKMGRCOLD_RESET 160
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/* 161-162 is reserved */
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#define S2FCOLD_RESET 163
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#define TIMESTAMPCOLD_RESET 164
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#define TAPCOLD_RESET 165
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#define HMCCOLD_RESET 166
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#define IOMGRCOLD_RESET 167
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/* NRSTMODRST */
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#define NRSTPINOE_RESET 192
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/* DBGMODRST */
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#define DBG_RESET 224
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#endif
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