Kever Yang 0132234160 clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register ... According to rk3288 trm, the clk_usbphy480m_gate is located at bit 14 of CRU_CLKGATE5_CON register. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2014-11-16 00:02:24 +01:00
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clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: fix rk3188 hsadc_frac definition	2014-11-07 23:41:14 +01:00
clk-rk3288.c	clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register	2014-11-16 00:02:24 +01:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: rockchip: disable unused clocks	2014-11-04 22:52:51 +01:00
clk.h	clk: rockchip: change PLL setting for better clock jitter	2014-10-29 20:27:20 +01:00
Makefile	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00