1fb2e4aab8
The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
99 lines
1.5 KiB
Plaintext
99 lines
1.5 KiB
Plaintext
Gate clock outputs
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* AXI gates ("allwinner,sun4i-axi-gates-clk")
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DRAM 0
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* AHB gates ("allwinner,sun7i-a20-ahb-gates-clk")
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USB0 0
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EHCI0 1
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OHCI0 2
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EHCI1 3
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OHCI1 4
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SS 5
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DMA 6
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BIST 7
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MMC0 8
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MMC1 9
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MMC2 10
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MMC3 11
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MS 12
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NAND 13
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SDRAM 14
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ACE 16
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EMAC 17
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TS 18
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SPI0 20
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SPI1 21
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SPI2 22
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SPI3 23
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SATA 25
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HSTIMER 28
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VE 32
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TVD 33
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TVE0 34
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TVE1 35
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LCD0 36
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LCD1 37
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CSI0 40
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CSI1 41
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HDMI1 42
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HDMI0 43
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DE_BE0 44
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DE_BE1 45
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DE_FE1 46
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DE_FE1 47
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GMAC 49
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MP 50
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MALI400 52
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* APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk")
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CODEC 0
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SPDIF 1
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AC97 2
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IIS0 3
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IIS1 4
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PIO 5
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IR0 6
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IR1 7
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IIS2 8
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KEYPAD 10
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* APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk")
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I2C0 0
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I2C1 1
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I2C2 2
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I2C3 3
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CAN 4
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SCR 5
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PS20 6
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PS21 7
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I2C4 15
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UART0 16
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UART1 17
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UART2 18
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UART3 19
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UART4 20
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UART5 21
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UART6 22
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UART7 23
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Notation:
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[*]: The datasheet didn't mention these, but they are present on AW code
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[**]: The datasheet had this marked as "NC" but they are used on AW code
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