2bfdd113d0
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd:
[ 4.854337] m25p80@0 enforce active low on chipselect handle
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
942 lines
23 KiB
Plaintext
942 lines
23 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright 2016-2020 Toradex
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*/
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/ {
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bl: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_bl_on>;
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pwms = <&pwm1 0 5000000 0>;
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enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
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};
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reg_module_3v3: regulator-module-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "+V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_module_3v3_avdd: regulator-module-3v3-avdd {
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compatible = "regulator-fixed";
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regulator-name = "+V3.3_AVDD_AUDIO";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx7-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,cpu {
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sound-dai = <&sai1>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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};
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};
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};
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&adc1 {
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vref-supply = <®_DCDC3>;
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};
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&adc2 {
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vref-supply = <®_DCDC3>;
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};
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&cpu0 {
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cpu-supply = <®_DCDC2>;
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
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cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
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};
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&fec1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet1>;
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pinctrl-1 = <&pinctrl_enet1_sleep>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
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clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rmii";
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phy-supply = <®_LDO1>;
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fsl,magic-packet;
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "disabled";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "disabled";
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};
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&gpio1 {
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gpio-line-names = "SODIMM_43",
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"SODIMM_45",
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"SODIMM_135",
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"SODIMM_22",
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"",
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"",
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"SODIMM_37",
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"SODIMM_29",
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"SODIMM_59",
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"SODIMM_28",
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"SODIMM_30",
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"SODIMM_67",
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"",
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"",
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"SODIMM_188",
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"SODIMM_178";
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};
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&gpio2 {
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gpio-line-names = "SODIMM_111",
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"SODIMM_113",
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"SODIMM_115",
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"SODIMM_117",
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"SODIMM_119",
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"SODIMM_121",
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"SODIMM_123",
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"SODIMM_125",
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"SODIMM_91",
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"SODIMM_89",
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"SODIMM_105",
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"SODIMM_152",
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"SODIMM_150",
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"SODIMM_95",
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"SODIMM_126",
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"SODIMM_107",
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"SODIMM_114",
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"SODIMM_116",
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"SODIMM_118",
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"SODIMM_120",
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"SODIMM_122",
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"SODIMM_124",
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"SODIMM_127",
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"SODIMM_130",
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"SODIMM_132",
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"SODIMM_134",
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"SODIMM_133",
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"SODIMM_104",
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"SODIMM_106",
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"SODIMM_110",
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"SODIMM_112",
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"SODIMM_128";
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};
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&gpio3 {
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gpio-line-names = "SODIMM_56",
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"SODIMM_44",
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"SODIMM_68",
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"SODIMM_82",
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"SODIMM_93",
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"SODIMM_76",
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"SODIMM_70",
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"SODIMM_60",
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"SODIMM_58",
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"SODIMM_78",
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"SODIMM_72",
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"SODIMM_80",
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"SODIMM_46",
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"SODIMM_62",
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"SODIMM_48",
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"SODIMM_74",
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"SODIMM_50",
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"SODIMM_52",
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"SODIMM_54",
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"SODIMM_66",
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"SODIMM_64",
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"SODIMM_57",
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"SODIMM_61",
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"SODIMM_136",
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"SODIMM_138",
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"SODIMM_140",
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"SODIMM_142",
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"SODIMM_144",
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"SODIMM_146";
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};
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&gpio4 {
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gpio-line-names = "SODIMM_35",
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"SODIMM_33",
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"SODIMM_38",
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"SODIMM_36",
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"SODIMM_21",
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"SODIMM_19",
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"SODIMM_131",
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"SODIMM_129",
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"SODIMM_90",
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"SODIMM_92",
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"SODIMM_88",
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"SODIMM_86",
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"SODIMM_81",
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"SODIMM_94",
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"SODIMM_96",
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"SODIMM_75",
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"SODIMM_101",
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"SODIMM_103",
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"SODIMM_79",
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"SODIMM_97",
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"SODIMM_67",
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"SODIMM_59",
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"SODIMM_85",
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"SODIMM_65";
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};
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&gpio5 {
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gpio-line-names = "SODIMM_69",
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"SODIMM_71",
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"SODIMM_73",
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"SODIMM_47",
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"SODIMM_190",
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"SODIMM_192",
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"SODIMM_49",
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"SODIMM_51",
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"SODIMM_53",
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"",
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"",
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"SODIMM_98",
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"SODIMM_184",
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"SODIMM_186",
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"SODIMM_23",
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"SODIMM_31",
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"SODIMM_100",
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"SODIMM_102";
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};
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&gpio6 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SODIMM_169",
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"",
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"",
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"",
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"SODIMM_77",
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"SODIMM_24",
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"",
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"SODIMM_25",
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"SODIMM_27",
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"SODIMM_32",
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"SODIMM_34";
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};
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&gpio7 {
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gpio-line-names = "",
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"",
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"SODIMM_63",
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"SODIMM_55",
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"",
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"",
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"",
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"",
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"SODIMM_196",
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"SODIMM_194",
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"",
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"SODIMM_99",
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"",
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"",
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"SODIMM_137";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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fsl,use-minimum-ecc;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
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pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
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scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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codec: sgtl5000@a {
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compatible = "fsl,sgtl5000";
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#sound-dai-cells = <0>;
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reg = <0x0a>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1_mclk>;
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VDDA-supply = <®_module_3v3_avdd>;
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VDDIO-supply = <®_module_3v3>;
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VDDD-supply = <®_DCDC3>;
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};
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ad7879@2c {
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compatible = "adi,ad7879-1";
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reg = <0x2c>;
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interrupt-parent = <&gpio1>;
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interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
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touchscreen-max-pressure = <4096>;
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adi,resistance-plate-x = <120>;
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adi,first-conversion-delay = /bits/ 8 <3>;
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adi,acquisition-time = /bits/ 8 <1>;
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adi,median-filter-size = /bits/ 8 <2>;
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adi,averaging = /bits/ 8 <1>;
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adi,conversion-interval = /bits/ 8 <255>;
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};
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pmic@33 {
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compatible = "ricoh,rn5t567";
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reg = <0x33>;
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regulators {
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reg_DCDC1: DCDC1 { /* V1.0_SOC */
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_DCDC2: DCDC2 { /* V1.1_ARM */
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regulator-min-microvolt = <975000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_DCDC3: DCDC3 { /* V1.8 */
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_DCDC4: DCDC4 { /* V1.35_DRAM */
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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reg_LDO2: LDO2 { /* +V1.8_SD */
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_LDO4: LDO4 { /* V1.8_LPSR */
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-1 = <&pinctrl_i2c4_recovery>;
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scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat
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&pinctrl_lcdif_ctrl>;
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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};
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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};
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®_1p0d {
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vin-supply = <®_DCDC3>;
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
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assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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uart-has-rtscts;
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fsl,dte-mode;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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uart-has-rtscts;
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fsl,dte-mode;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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fsl,dte-mode;
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};
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&usbotg1 {
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dr_mode = "host";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
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cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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disable-wp;
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vqmmc-supply = <®_LDO2>;
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
|
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bus-width = <8>;
|
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fsl,tuning-step = <2>;
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vmmc-supply = <®_module_3v3>;
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vqmmc-supply = <®_DCDC3>;
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non-removable;
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sdhci-caps-mask = <0x80000000 0x0>;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
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&pinctrl_gpio7 &pinctrl_usbc_det>;
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|
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pinctrl_gpio1: gpio1-grp {
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fsl,pins = <
|
|
MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
|
|
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
|
|
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
|
|
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
|
|
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
|
|
MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
|
|
MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
|
|
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
|
|
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
|
|
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
|
|
MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
|
|
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
|
|
MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
|
|
MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
|
|
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
|
|
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
|
|
MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
|
|
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
|
|
MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
|
|
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
|
|
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
|
|
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
|
|
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
|
|
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
|
|
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
|
|
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
|
|
MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
|
|
MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
|
|
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
|
|
MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
|
|
MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
|
|
MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
|
|
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
|
|
MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
|
|
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
|
|
MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
|
|
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
|
|
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
|
|
MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
|
|
MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
|
|
fsl,pins = <
|
|
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
|
|
MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
|
|
MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
|
|
MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
|
|
MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
|
|
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
|
|
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
|
|
MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
|
|
MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
|
|
MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
|
|
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
|
|
MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
|
|
MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
|
|
MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
|
|
MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
|
|
MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
|
|
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
|
|
MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_can_int: can-int-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet1: enet1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
|
|
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
|
|
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
|
|
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
|
|
|
|
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
|
|
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
|
|
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
|
|
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
|
|
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
|
|
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet1_sleep: enet1sleepgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
|
|
MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
|
|
MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
|
|
MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
|
|
|
|
MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
|
|
MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
|
|
MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
|
|
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
|
|
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
|
|
MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
|
|
>;
|
|
};
|
|
|
|
pinctrl_ecspi3_cs: ecspi3-cs-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_ecspi3: ecspi3-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
|
|
MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
|
|
MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
|
|
MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
|
|
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_bl_on: gpio-bl-on {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpmi_nand: gpmi-nand-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
|
|
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
|
|
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
|
|
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
|
|
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
|
|
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
|
|
MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
|
|
MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
|
|
MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
|
|
MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
|
|
MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
|
|
MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
|
|
MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
|
|
MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
|
|
MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4_recovery: i2c4-recoverygrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
|
|
MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_dat: lcdif-dat-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
|
|
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
|
|
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
|
|
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
|
|
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
|
|
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
|
|
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
|
|
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
|
|
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
|
|
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
|
|
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
|
|
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
|
|
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
|
|
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
|
|
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
|
|
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
|
|
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
|
|
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
|
|
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
|
|
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
|
|
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
|
|
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
|
|
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
|
|
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
|
|
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
|
|
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
|
|
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm3: pwm3-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm4: pwm4-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
|
|
MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
|
|
MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
|
|
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
|
|
MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
|
|
MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
|
|
MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
|
|
MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
|
|
>;
|
|
};
|
|
pinctrl_uart3: uart3-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
|
|
MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbc_det: gpio-usbc-det {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbh_reg: gpio-usbh-vbus {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai1: sai1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
|
|
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
|
|
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
|
|
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai1_mclk: sai1grp_mclk {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
|
|
>;
|
|
};
|
|
};
|
|
|
|
&iomuxc_lpsr {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio_lpsr>;
|
|
|
|
pinctrl_gpio_lpsr: gpio1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
|
|
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpiokeys: gpiokeysgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
|
|
MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_recovery: i2c1-recoverygrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
|
|
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_cd_usdhc1: usdhc1-cd-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
|
|
MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */
|
|
>;
|
|
};
|
|
};
|