drm bridges added by meson_encoder_hdmi_init and meson_encoder_cvbs_init were not manually removed at module unload time, which caused dangling references to freed memory to remain linked in the global bridge_list. When loading the driver modules back in, the same functions would again call drm_bridge_add, and when traversing the global bridge_list, would end up peeking into freed memory. Once again KASAN revealed the problem: [ +0.000095] ============================================================= [ +0.000008] BUG: KASAN: use-after-free in __list_add_valid+0x9c/0x120 [ +0.000018] Read of size 8 at addr ffff00003da291f0 by task modprobe/2483 [ +0.000018] CPU: 3 PID: 2483 Comm: modprobe Tainted: G C O 5.19.0-rc6-lrmbkasan+ #1 [ +0.000011] Hardware name: Hardkernel ODROID-N2Plus (DT) [ +0.000008] Call trace: [ +0.000006] dump_backtrace+0x1ec/0x280 [ +0.000012] show_stack+0x24/0x80 [ +0.000008] dump_stack_lvl+0x98/0xd4 [ +0.000011] print_address_description.constprop.0+0x80/0x520 [ +0.000011] print_report+0x128/0x260 [ +0.000008] kasan_report+0xb8/0xfc [ +0.000008] __asan_report_load8_noabort+0x3c/0x50 [ +0.000009] __list_add_valid+0x9c/0x120 [ +0.000009] drm_bridge_add+0x6c/0x104 [drm] [ +0.000165] dw_hdmi_probe+0x1900/0x2360 [dw_hdmi] [ +0.000022] meson_dw_hdmi_bind+0x520/0x814 [meson_dw_hdmi] [ +0.000014] component_bind+0x174/0x520 [ +0.000012] component_bind_all+0x1a8/0x38c [ +0.000010] meson_drv_bind_master+0x5e8/0xb74 [meson_drm] [ +0.000032] meson_drv_bind+0x20/0x2c [meson_drm] [ +0.000027] try_to_bring_up_aggregate_device+0x19c/0x390 [ +0.000010] component_master_add_with_match+0x1c8/0x284 [ +0.000009] meson_drv_probe+0x274/0x280 [meson_drm] [ +0.000026] platform_probe+0xd0/0x220 [ +0.000009] really_probe+0x3ac/0xa80 [ +0.000009] __driver_probe_device+0x1f8/0x400 [ +0.000009] driver_probe_device+0x68/0x1b0 [ +0.000009] __driver_attach+0x20c/0x480 [ +0.000008] bus_for_each_dev+0x114/0x1b0 [ +0.000009] driver_attach+0x48/0x64 [ +0.000008] bus_add_driver+0x390/0x564 [ +0.000009] driver_register+0x1a8/0x3e4 [ +0.000009] __platform_driver_register+0x6c/0x94 [ +0.000008] meson_drm_platform_driver_init+0x3c/0x1000 [meson_drm] [ +0.000027] do_one_initcall+0xc4/0x2b0 [ +0.000011] do_init_module+0x154/0x570 [ +0.000011] load_module+0x1a78/0x1ea4 [ +0.000008] __do_sys_init_module+0x184/0x1cc [ +0.000009] __arm64_sys_init_module+0x78/0xb0 [ +0.000009] invoke_syscall+0x74/0x260 [ +0.000009] el0_svc_common.constprop.0+0xcc/0x260 [ +0.000008] do_el0_svc+0x50/0x70 [ +0.000007] el0_svc+0x68/0x1a0 [ +0.000012] el0t_64_sync_handler+0x11c/0x150 [ +0.000008] el0t_64_sync+0x18c/0x190 [ +0.000016] Allocated by task 879: [ +0.000008] kasan_save_stack+0x2c/0x5c [ +0.000011] __kasan_kmalloc+0x90/0xd0 [ +0.000007] __kmalloc+0x278/0x4a0 [ +0.000011] mpi_resize+0x13c/0x1d0 [ +0.000011] mpi_powm+0xd24/0x1570 [ +0.000009] rsa_enc+0x1a4/0x30c [ +0.000009] pkcs1pad_verify+0x3f0/0x580 [ +0.000009] public_key_verify_signature+0x7a8/0xba4 [ +0.000010] public_key_verify_signature_2+0x40/0x60 [ +0.000008] verify_signature+0xb4/0x114 [ +0.000008] pkcs7_validate_trust_one.constprop.0+0x3b8/0x574 [ +0.000009] pkcs7_validate_trust+0xb8/0x15c [ +0.000008] verify_pkcs7_message_sig+0xec/0x1b0 [ +0.000012] verify_pkcs7_signature+0x78/0xac [ +0.000007] mod_verify_sig+0x110/0x190 [ +0.000009] module_sig_check+0x114/0x1e0 [ +0.000009] load_module+0xa0/0x1ea4 [ +0.000008] __do_sys_init_module+0x184/0x1cc [ +0.000008] __arm64_sys_init_module+0x78/0xb0 [ +0.000008] invoke_syscall+0x74/0x260 [ +0.000009] el0_svc_common.constprop.0+0x1a8/0x260 [ +0.000008] do_el0_svc+0x50/0x70 [ +0.000007] el0_svc+0x68/0x1a0 [ +0.000009] el0t_64_sync_handler+0x11c/0x150 [ +0.000009] el0t_64_sync+0x18c/0x190 [ +0.000013] Freed by task 2422: [ +0.000008] kasan_save_stack+0x2c/0x5c [ +0.000009] kasan_set_track+0x2c/0x40 [ +0.000007] kasan_set_free_info+0x28/0x50 [ +0.000009] ____kasan_slab_free+0x128/0x1d4 [ +0.000008] __kasan_slab_free+0x18/0x24 [ +0.000007] slab_free_freelist_hook+0x108/0x230 [ +0.000010] kfree+0x110/0x35c [ +0.000008] release_nodes+0xf0/0x16c [ +0.000009] devres_release_group+0x180/0x270 [ +0.000008] take_down_aggregate_device+0xcc/0x160 [ +0.000010] component_del+0x18c/0x360 [ +0.000009] meson_dw_hdmi_remove+0x28/0x40 [meson_dw_hdmi] [ +0.000013] platform_remove+0x64/0xb0 [ +0.000008] device_remove+0xb8/0x154 [ +0.000009] device_release_driver_internal+0x398/0x5b0 [ +0.000009] driver_detach+0xac/0x1b0 [ +0.000009] bus_remove_driver+0x158/0x29c [ +0.000008] driver_unregister+0x70/0xb0 [ +0.000009] platform_driver_unregister+0x20/0x2c [ +0.000007] meson_dw_hdmi_platform_driver_exit+0x1c/0x30 [meson_dw_hdmi] [ +0.000012] __do_sys_delete_module+0x288/0x400 [ +0.000009] __arm64_sys_delete_module+0x5c/0x80 [ +0.000009] invoke_syscall+0x74/0x260 [ +0.000008] el0_svc_common.constprop.0+0xcc/0x260 [ +0.000008] do_el0_svc+0x50/0x70 [ +0.000007] el0_svc+0x68/0x1a0 [ +0.000008] el0t_64_sync_handler+0x11c/0x150 [ +0.000009] el0t_64_sync+0x18c/0x190 [ +0.000013] The buggy address belongs to the object at ffff00003da29000 which belongs to the cache kmalloc-1k of size 1024 [ +0.000008] The buggy address is located 496 bytes inside of 1024-byte region [ffff00003da29000, ffff00003da29400) [ +0.000015] The buggy address belongs to the physical page: [ +0.000009] page:fffffc0000f68a00 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x3da28 [ +0.000012] head:fffffc0000f68a00 order:3 compound_mapcount:0 compound_pincount:0 [ +0.000009] flags: 0xffff00000010200(slab|head|node=0|zone=0|lastcpupid=0xffff) [ +0.000019] raw: 0ffff00000010200 fffffc0000eb5c08 fffffc0000d96608 ffff000000002a80 [ +0.000008] raw: 0000000000000000 00000000000a000a 00000001ffffffff 0000000000000000 [ +0.000008] page dumped because: kasan: bad access detected [ +0.000011] Memory state around the buggy address: [ +0.000009] ffff00003da29080: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ +0.000007] ffff00003da29100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ +0.000007] >ffff00003da29180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ +0.000007] ^ [ +0.000008] ffff00003da29200: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ +0.000006] ffff00003da29280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ +0.000007] ================================================================== Fix by keeping track of which encoders were initialised in the meson_drm structure and manually removing their bridges at aggregate driver's unbind time. Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220920222842.1053234-1-adrian.larumbe@collabora.com
299 lines
8.8 KiB
C
299 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/export.h>
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#include <linux/of_graph.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_bridge_connector.h>
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#include <drm/drm_device.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "meson_registers.h"
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#include "meson_vclk.h"
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#include "meson_encoder_cvbs.h"
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/* HHI VDAC Registers */
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
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struct meson_encoder_cvbs {
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struct drm_encoder encoder;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct meson_drm *priv;
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};
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#define bridge_to_meson_encoder_cvbs(x) \
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container_of(x, struct meson_encoder_cvbs, bridge)
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/* Supported Modes */
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struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = {
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{ /* PAL */
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.enci = &meson_cvbs_enci_pal,
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.mode = {
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DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
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720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
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DRM_MODE_FLAG_INTERLACE),
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.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
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},
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},
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{ /* NTSC */
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.enci = &meson_cvbs_enci_ntsc,
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.mode = {
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DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
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720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
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DRM_MODE_FLAG_INTERLACE),
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.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
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},
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},
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};
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static const struct meson_cvbs_mode *
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meson_cvbs_get_mode(const struct drm_display_mode *req_mode)
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{
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int i;
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for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
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struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
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if (drm_mode_match(req_mode, &meson_mode->mode,
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DRM_MODE_MATCH_TIMINGS |
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DRM_MODE_MATCH_CLOCK |
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DRM_MODE_MATCH_FLAGS |
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DRM_MODE_MATCH_3D_FLAGS))
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return meson_mode;
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}
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return NULL;
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}
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static int meson_encoder_cvbs_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct meson_encoder_cvbs *meson_encoder_cvbs =
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bridge_to_meson_encoder_cvbs(bridge);
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return drm_bridge_attach(bridge->encoder, meson_encoder_cvbs->next_bridge,
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&meson_encoder_cvbs->bridge, flags);
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}
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static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge,
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struct drm_connector *connector)
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{
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struct meson_encoder_cvbs *meson_encoder_cvbs =
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bridge_to_meson_encoder_cvbs(bridge);
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struct meson_drm *priv = meson_encoder_cvbs->priv;
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struct drm_display_mode *mode;
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int i;
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for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
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struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
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mode = drm_mode_duplicate(priv->drm, &meson_mode->mode);
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if (!mode) {
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dev_err(priv->dev, "Failed to create a new display mode\n");
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return 0;
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}
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drm_mode_probed_add(connector, mode);
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}
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return i;
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}
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static int meson_encoder_cvbs_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_info *display_info,
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const struct drm_display_mode *mode)
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{
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if (meson_cvbs_get_mode(mode))
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return MODE_OK;
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return MODE_BAD;
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}
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static int meson_encoder_cvbs_atomic_check(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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if (meson_cvbs_get_mode(&crtc_state->mode))
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return 0;
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return -EINVAL;
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}
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static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state)
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{
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struct meson_encoder_cvbs *encoder_cvbs = bridge_to_meson_encoder_cvbs(bridge);
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struct drm_atomic_state *state = bridge_state->base.state;
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struct meson_drm *priv = encoder_cvbs->priv;
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const struct meson_cvbs_mode *meson_mode;
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struct drm_connector_state *conn_state;
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struct drm_crtc_state *crtc_state;
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struct drm_connector *connector;
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connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
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if (WARN_ON(!connector))
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return;
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conn_state = drm_atomic_get_new_connector_state(state, connector);
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if (WARN_ON(!conn_state))
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return;
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crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
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if (WARN_ON(!crtc_state))
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return;
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meson_mode = meson_cvbs_get_mode(&crtc_state->adjusted_mode);
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if (WARN_ON(!meson_mode))
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return;
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meson_venci_cvbs_mode_set(priv, meson_mode->enci);
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/* Setup 27MHz vclk2 for ENCI and VDAC */
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meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
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MESON_VCLK_CVBS, MESON_VCLK_CVBS,
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MESON_VCLK_CVBS, MESON_VCLK_CVBS,
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true);
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/* VDAC0 source is not from ATV */
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writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
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priv->io_base + _REG(VENC_VDAC_DACSEL0));
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
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} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
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} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
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}
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}
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static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state)
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{
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struct meson_encoder_cvbs *meson_encoder_cvbs =
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bridge_to_meson_encoder_cvbs(bridge);
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struct meson_drm *priv = meson_encoder_cvbs->priv;
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/* Disable CVBS VDAC */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
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} else {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
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}
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}
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static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = {
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.attach = meson_encoder_cvbs_attach,
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.mode_valid = meson_encoder_cvbs_mode_valid,
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.get_modes = meson_encoder_cvbs_get_modes,
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.atomic_enable = meson_encoder_cvbs_atomic_enable,
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.atomic_disable = meson_encoder_cvbs_atomic_disable,
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.atomic_check = meson_encoder_cvbs_atomic_check,
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.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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.atomic_reset = drm_atomic_helper_bridge_reset,
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};
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int meson_encoder_cvbs_init(struct meson_drm *priv)
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{
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struct drm_device *drm = priv->drm;
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struct meson_encoder_cvbs *meson_encoder_cvbs;
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struct drm_connector *connector;
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struct device_node *remote;
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int ret;
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meson_encoder_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_encoder_cvbs), GFP_KERNEL);
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if (!meson_encoder_cvbs)
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return -ENOMEM;
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/* CVBS Connector Bridge */
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remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
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if (!remote) {
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dev_info(drm->dev, "CVBS Output connector not available\n");
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return 0;
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}
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meson_encoder_cvbs->next_bridge = of_drm_find_bridge(remote);
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of_node_put(remote);
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if (!meson_encoder_cvbs->next_bridge) {
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dev_err(priv->dev, "Failed to find CVBS Connector bridge\n");
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return -EPROBE_DEFER;
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}
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/* CVBS Encoder Bridge */
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meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs;
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meson_encoder_cvbs->bridge.of_node = priv->dev->of_node;
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meson_encoder_cvbs->bridge.type = DRM_MODE_CONNECTOR_Composite;
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meson_encoder_cvbs->bridge.ops = DRM_BRIDGE_OP_MODES;
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meson_encoder_cvbs->bridge.interlace_allowed = true;
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drm_bridge_add(&meson_encoder_cvbs->bridge);
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meson_encoder_cvbs->priv = priv;
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/* Encoder */
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ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder,
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DRM_MODE_ENCODER_TVDAC);
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if (ret) {
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dev_err(priv->dev, "Failed to init CVBS encoder: %d\n", ret);
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return ret;
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}
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meson_encoder_cvbs->encoder.possible_crtcs = BIT(0);
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/* Attach CVBS Encoder Bridge to Encoder */
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ret = drm_bridge_attach(&meson_encoder_cvbs->encoder, &meson_encoder_cvbs->bridge, NULL,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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if (ret) {
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dev_err(priv->dev, "Failed to attach bridge: %d\n", ret);
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return ret;
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}
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/* Initialize & attach Bridge Connector */
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connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder);
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if (IS_ERR(connector)) {
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dev_err(priv->dev, "Unable to create CVBS bridge connector\n");
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return PTR_ERR(connector);
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}
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drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder);
|
|
|
|
priv->encoders[MESON_ENC_CVBS] = meson_encoder_cvbs;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void meson_encoder_cvbs_remove(struct meson_drm *priv)
|
|
{
|
|
struct meson_encoder_cvbs *meson_encoder_cvbs;
|
|
|
|
if (priv->encoders[MESON_ENC_CVBS]) {
|
|
meson_encoder_cvbs = priv->encoders[MESON_ENC_CVBS];
|
|
drm_bridge_remove(&meson_encoder_cvbs->bridge);
|
|
drm_bridge_remove(meson_encoder_cvbs->next_bridge);
|
|
}
|
|
}
|