d7164a5048
Accessing the TypeC DKL PHY registers during modeset-commit, -verification, DP link-retraining and AUX power well toggling is racy due to these code paths being concurrent and the PHY register bank selection register (HIP_INDEX_REG) being shared between PHY instances (aka TC ports) and the bank selection being not atomic wrt. the actual PHY register access. Add the required locking around each PHY register bank selection-> register access sequence. Kudos to Ville for noticing the race conditions. v2: - Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani) - Make the DKL_REG_TC_PORT macro independent of PHY internals. - Move initing the DKL PHY lock to a more logical place. v3: - Fix parameter reuse in the DKL_REG_TC_PORT definition. - Document the usage of phy_lock. v4: - Fix adding TC_PORT_1 offset in the DKL_REG_TC_PORT definition. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: <stable@vger.kernel.org> # v5.5+ Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221025114457.2191004-1-imre.deak@intel.com (cherry picked from commit 89cb0ba4ceee6bed1059904859c5723b3f39da68) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display.h"
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#include "intel_dkl_phy.h"
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static void
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dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
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{
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enum tc_port tc_port = DKL_REG_TC_PORT(reg);
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drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
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intel_de_write(i915,
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HIP_INDEX_REG(tc_port),
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HIP_INDEX_VAL(tc_port, idx));
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}
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/**
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* intel_dkl_phy_read - read a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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*
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* Read the @reg Dekel PHY register.
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*
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* Returns the read value.
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*/
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u32
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intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln)
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{
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u32 val;
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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val = intel_de_read(i915, reg);
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spin_unlock(&i915->display.dkl.phy_lock);
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return val;
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}
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/**
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* intel_dkl_phy_write - write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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* @val: value to write
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*
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* Write @val to the @reg Dekel PHY register.
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*/
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void
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intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_write(i915, reg, val);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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/**
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* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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* @clear: mask to clear
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* @set: mask to set
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*
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* Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing
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* this value back to the register if the value differs from the read one.
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*/
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void
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intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_rmw(i915, reg, clear, set);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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/**
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* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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*
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* Read the @reg Dekel PHY register without returning the read value.
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*/
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void
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_posting_read(i915, reg);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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