forked from Minki/linux
cca7b7d5f1
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com
120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-alpha-pll.h"
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static const u8 ipq_pll_offsets[] = {
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[PLL_OFF_L_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL] = 0x10,
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[PLL_OFF_USER_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL] = 0x20,
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[PLL_OFF_CONFIG_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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[PLL_OFF_TEST_CTL] = 0x30,
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[PLL_OFF_TEST_CTL_U] = 0x34,
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};
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static struct clk_alpha_pll ipq_pll = {
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.offset = 0x0,
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.regs = ipq_pll_offsets,
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.enable_reg = 0x0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "a53pll",
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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},
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};
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static const struct alpha_pll_config ipq6018_pll_config = {
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.l = 0x37,
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.config_ctl_val = 0x240d4828,
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.config_ctl_hi_val = 0x6,
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.early_output_mask = BIT(3),
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.aux2_output_mask = BIT(2),
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.aux_output_mask = BIT(1),
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.main_output_mask = BIT(0),
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.test_ctl_val = 0x1c0000C0,
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.test_ctl_hi_val = 0x4000,
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};
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static const struct alpha_pll_config ipq8074_pll_config = {
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.l = 0x48,
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.config_ctl_val = 0x200d4828,
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.config_ctl_hi_val = 0x6,
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.early_output_mask = BIT(3),
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.aux2_output_mask = BIT(2),
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.aux_output_mask = BIT(1),
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.main_output_mask = BIT(0),
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.test_ctl_val = 0x1c000000,
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.test_ctl_hi_val = 0x4000,
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};
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static const struct regmap_config ipq_pll_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x40,
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.fast_io = true,
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};
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static int apss_ipq_pll_probe(struct platform_device *pdev)
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{
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const struct alpha_pll_config *ipq_pll_config;
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ipq_pll_config = of_device_get_match_data(&pdev->dev);
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if (!ipq_pll_config)
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return -ENODEV;
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clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
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ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&ipq_pll.clkr.hw);
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}
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static const struct of_device_id apss_ipq_pll_match_table[] = {
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{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
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{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
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{ }
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};
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MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
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static struct platform_driver apss_ipq_pll_driver = {
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.probe = apss_ipq_pll_probe,
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.driver = {
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.name = "qcom-ipq-apss-pll",
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.of_match_table = apss_ipq_pll_match_table,
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},
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};
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module_platform_driver(apss_ipq_pll_driver);
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MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
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MODULE_LICENSE("GPL v2");
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