b56bae2dd6
Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
12 lines
295 B
Plaintext
12 lines
295 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config COMMON_CLK_PIC32
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def_bool COMMON_CLK && MACH_PIC32
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config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
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depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST
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select AUXILIARY_BUS
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help
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Supports Clock Configuration for PolarFire SoC
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