forked from Minki/linux
97d485edc1
Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the hexagon CPU core out of reset. However, it is possible to change the configuration, in which case this driver will initialize the bus. In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design. Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors. Signed-off-by: Michael Srba <Michael.Srba@seznam.cz> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz
256 lines
8.2 KiB
Plaintext
256 lines
8.2 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
#
|
|
# Bus Devices
|
|
#
|
|
|
|
menu "Bus devices"
|
|
|
|
config ARM_CCI
|
|
bool
|
|
|
|
config ARM_CCI400_COMMON
|
|
bool
|
|
select ARM_CCI
|
|
|
|
config ARM_CCI400_PORT_CTRL
|
|
bool
|
|
depends on ARM && OF && CPU_V7
|
|
select ARM_CCI400_COMMON
|
|
help
|
|
Low level power management driver for CCI400 cache coherent
|
|
interconnect for ARM platforms.
|
|
|
|
config ARM_INTEGRATOR_LM
|
|
bool "ARM Integrator Logic Module bus"
|
|
depends on HAS_IOMEM
|
|
depends on ARCH_INTEGRATOR || COMPILE_TEST
|
|
default ARCH_INTEGRATOR
|
|
help
|
|
Say y here to enable support for the ARM Logic Module bus
|
|
found on the ARM Integrator AP (Application Platform)
|
|
|
|
config BRCMSTB_GISB_ARB
|
|
tristate "Broadcom STB GISB bus arbiter"
|
|
depends on ARM || ARM64 || MIPS
|
|
default ARCH_BRCMSTB || BMIPS_GENERIC
|
|
help
|
|
Driver for the Broadcom Set Top Box System-on-a-chip internal bus
|
|
arbiter. This driver provides timeout and target abort error handling
|
|
and internal bus master decoding.
|
|
|
|
config BT1_APB
|
|
bool "Baikal-T1 APB-bus driver"
|
|
depends on MIPS_BAIKAL_T1 || COMPILE_TEST
|
|
select REGMAP_MMIO
|
|
help
|
|
Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
|
|
IO requests are routed to this bus by means of the DW AMBA 3 AXI
|
|
Interconnect. In case of any APB protocol collisions, slave device
|
|
not responding on timeout an IRQ is raised with an erroneous address
|
|
reported to the APB terminator (APB Errors Handler Block). This
|
|
driver provides the interrupt handler to detect the erroneous
|
|
address, prints an error message about the address fault, updates an
|
|
errors counter. The counter and the APB-bus operations timeout can be
|
|
accessed via corresponding sysfs nodes.
|
|
|
|
config BT1_AXI
|
|
bool "Baikal-T1 AXI-bus driver"
|
|
depends on MIPS_BAIKAL_T1 || COMPILE_TEST
|
|
select MFD_SYSCON
|
|
help
|
|
AXI3-bus is the main communication bus connecting all high-speed
|
|
peripheral IP-cores with RAM controller and with MIPS P5600 cores on
|
|
Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
|
|
Interconnect (so called AXI Main Interconnect) routing IO requests
|
|
from one SoC block to another. This driver provides a way to detect
|
|
any bus protocol errors and device not responding situations by
|
|
means of an embedded on top of the interconnect errors handler
|
|
block (EHB). AXI Interconnect QoS arbitration tuning is currently
|
|
unsupported.
|
|
|
|
config MOXTET
|
|
tristate "CZ.NIC Turris Mox module configuration bus"
|
|
depends on SPI_MASTER && OF
|
|
help
|
|
Say yes here to add support for the module configuration bus found
|
|
on CZ.NIC's Turris Mox. This is needed for the ability to discover
|
|
the order in which the modules are connected and to get/set some of
|
|
their settings. For example the GPIOs on Mox SFP module are
|
|
configured through this bus.
|
|
|
|
config HISILICON_LPC
|
|
bool "Support for ISA I/O space on HiSilicon Hip06/7"
|
|
depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC)
|
|
depends on HAS_IOMEM
|
|
select INDIRECT_PIO if ARM64
|
|
help
|
|
Driver to enable I/O access to devices attached to the Low Pin
|
|
Count bus on the HiSilicon Hip06/7 SoC.
|
|
|
|
config IMX_WEIM
|
|
bool "Freescale EIM DRIVER"
|
|
depends on ARCH_MXC
|
|
help
|
|
Driver for i.MX WEIM controller.
|
|
The WEIM(Wireless External Interface Module) works like a bus.
|
|
You can attach many different devices on it, such as NOR, onenand.
|
|
|
|
config INTEL_IXP4XX_EB
|
|
bool "Intel IXP4xx expansion bus interface driver"
|
|
depends on HAS_IOMEM
|
|
depends on ARCH_IXP4XX || COMPILE_TEST
|
|
default ARCH_IXP4XX
|
|
select MFD_SYSCON
|
|
help
|
|
Driver for the Intel IXP4xx expansion bus interface. The driver is
|
|
needed to set up various chip select configuration parameters before
|
|
devices on the expansion bus can be discovered.
|
|
|
|
config MIPS_CDMM
|
|
bool "MIPS Common Device Memory Map (CDMM) Driver"
|
|
depends on CPU_MIPSR2 || CPU_MIPSR5
|
|
help
|
|
Driver needed for the MIPS Common Device Memory Map bus in MIPS
|
|
cores. This bus is for per-CPU tightly coupled devices such as the
|
|
Fast Debug Channel (FDC).
|
|
|
|
For this to work, either your bootloader needs to enable the CDMM
|
|
region at an unused physical address on the boot CPU, or else your
|
|
platform code needs to implement mips_cdmm_phys_base() (see
|
|
asm/cdmm.h).
|
|
|
|
config MVEBU_MBUS
|
|
bool
|
|
depends on PLAT_ORION
|
|
help
|
|
Driver needed for the MBus configuration on Marvell EBU SoCs
|
|
(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
|
|
|
|
config OMAP_INTERCONNECT
|
|
tristate "OMAP INTERCONNECT DRIVER"
|
|
depends on ARCH_OMAP2PLUS
|
|
|
|
help
|
|
Driver to enable OMAP interconnect error handling driver.
|
|
|
|
config OMAP_OCP2SCP
|
|
tristate "OMAP OCP2SCP DRIVER"
|
|
depends on ARCH_OMAP2PLUS
|
|
help
|
|
Driver to enable ocp2scp module which transforms ocp interface
|
|
protocol to scp protocol. In OMAP4, USB PHY is connected via
|
|
OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
|
|
OCP2SCP.
|
|
|
|
config QCOM_EBI2
|
|
bool "Qualcomm External Bus Interface 2 (EBI2)"
|
|
depends on HAS_IOMEM
|
|
depends on ARCH_QCOM || COMPILE_TEST
|
|
default ARCH_QCOM
|
|
help
|
|
Say y here to enable support for the Qualcomm External Bus
|
|
Interface 2, which can be used to connect things like NAND Flash,
|
|
SRAM, ethernet adapters, FPGAs and LCD displays.
|
|
|
|
config QCOM_SSC_BLOCK_BUS
|
|
bool "Qualcomm SSC Block Bus Init Driver"
|
|
depends on ARCH_QCOM
|
|
help
|
|
Say y here to enable support for initializing the bus that connects
|
|
the SSC block's internal bus to the cNoC (configurantion NoC) on
|
|
(some) qcom SoCs.
|
|
The SSC (Snapdragon Sensor Core) block contains a gpio controller,
|
|
i2c/spi/uart controllers, a hexagon core, and a clock controller
|
|
which provides clocks for the above.
|
|
|
|
config SUN50I_DE2_BUS
|
|
bool "Allwinner A64 DE2 Bus Driver"
|
|
default ARM64
|
|
depends on ARCH_SUNXI
|
|
select SUNXI_SRAM
|
|
help
|
|
Say y here to enable support for Allwinner A64 DE2 bus driver. It's
|
|
mostly transparent, but a SRAM region needs to be claimed in the SRAM
|
|
controller to make the all blocks in the DE2 part accessible.
|
|
|
|
config SUNXI_RSB
|
|
tristate "Allwinner sunXi Reduced Serial Bus Driver"
|
|
default MACH_SUN8I || MACH_SUN9I || ARM64
|
|
depends on ARCH_SUNXI
|
|
select REGMAP
|
|
help
|
|
Say y here to enable support for Allwinner's Reduced Serial Bus
|
|
(RSB) support. This controller is responsible for communicating
|
|
with various RSB based devices, such as AXP223, AXP8XX PMICs,
|
|
and AC100/AC200 ICs.
|
|
|
|
config TEGRA_ACONNECT
|
|
tristate "Tegra ACONNECT Bus Driver"
|
|
depends on ARCH_TEGRA_210_SOC
|
|
depends on OF && PM
|
|
help
|
|
Driver for the Tegra ACONNECT bus which is used to interface with
|
|
the devices inside the Audio Processing Engine (APE) for Tegra210.
|
|
|
|
config TEGRA_GMI
|
|
tristate "Tegra Generic Memory Interface bus driver"
|
|
depends on ARCH_TEGRA
|
|
help
|
|
Driver for the Tegra Generic Memory Interface bus which can be used
|
|
to attach devices such as NOR, UART, FPGA and more.
|
|
|
|
config TI_PWMSS
|
|
bool
|
|
default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM || TI_EQEP)
|
|
help
|
|
PWM Subsystem driver support for AM33xx SOC.
|
|
|
|
PWM submodules require PWM config space access from submodule
|
|
drivers and require common parent driver support.
|
|
|
|
config TI_SYSC
|
|
bool "TI sysc interconnect target module driver"
|
|
depends on ARCH_OMAP2PLUS
|
|
help
|
|
Generic driver for Texas Instruments interconnect target module
|
|
found on many TI SoCs.
|
|
|
|
config TS_NBUS
|
|
tristate "Technologic Systems NBUS Driver"
|
|
depends on SOC_IMX28
|
|
depends on OF_GPIO && PWM
|
|
help
|
|
Driver for the Technologic Systems NBUS which is used to interface
|
|
with the peripherals in the FPGA of the TS-4600 SoM.
|
|
|
|
config UNIPHIER_SYSTEM_BUS
|
|
tristate "UniPhier System Bus driver"
|
|
depends on ARCH_UNIPHIER && OF
|
|
default y
|
|
help
|
|
Support for UniPhier System Bus, a simple external bus. This is
|
|
needed to use on-board devices connected to UniPhier SoCs.
|
|
|
|
config VEXPRESS_CONFIG
|
|
tristate "Versatile Express configuration bus"
|
|
default y if ARCH_VEXPRESS
|
|
depends on ARM || ARM64
|
|
depends on OF
|
|
select REGMAP
|
|
help
|
|
Platform configuration infrastructure for the ARM Ltd.
|
|
Versatile Express.
|
|
|
|
config DA8XX_MSTPRI
|
|
bool "TI da8xx master peripheral priority driver"
|
|
depends on ARCH_DAVINCI_DA8XX
|
|
help
|
|
Driver for Texas Instruments da8xx master peripheral priority
|
|
configuration. Allows to adjust the priorities of all master
|
|
peripherals.
|
|
|
|
source "drivers/bus/fsl-mc/Kconfig"
|
|
source "drivers/bus/mhi/Kconfig"
|
|
|
|
endmenu
|