forked from Minki/linux
0fdebc5ec2
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-orion5x/rd88f5182-setup.c
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*
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* Marvell Orion-NAS Reference Design Setup
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include "common.h"
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#include "orion5x.h"
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/*****************************************************************************
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* RD-88F5182 Info
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****************************************************************************/
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/*
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* PCI
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*/
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#define RD88F5182_PCI_SLOT0_OFFS 7
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#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
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#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
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/*****************************************************************************
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* PCI
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****************************************************************************/
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static void __init rd88f5182_pci_preinit(void)
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{
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int pin;
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/*
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* Configure PCI GPIO IRQ pins
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*/
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pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
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if (gpio_request(pin, "PCI IntA") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
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}
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pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
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if (gpio_request(pin, "PCI IntB") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
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}
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}
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static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
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u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* PCI IRQs are connected via GPIOs
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*/
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switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
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case 0:
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if (pin == 1)
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
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else
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
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default:
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return -1;
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}
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}
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static struct hw_pci rd88f5182_pci __initdata = {
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.nr_controllers = 2,
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.preinit = rd88f5182_pci_preinit,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5182_pci_map_irq,
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};
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static int __init rd88f5182_pci_init(void)
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{
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if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
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pci_common_init(&rd88f5182_pci);
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return 0;
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}
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subsys_initcall(rd88f5182_pci_init);
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