forked from Minki/linux
498574970f
* A handful of DT updates for the PolarFire SOC. * A fix to correct the handling of write-only mappings. * m{vetndor,arcd,imp}id is now in /proc/cpuinfo * The SiFive L2 cache controller support has been refactored to also support L3 caches. There's also a handful of fixes, cleanups and improvements throughout the tree. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmNJiegTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiaW+D/9nN7JMKD4KbED8MUgRVcs+TS4MQk5J QkjmAXme7w2H1+T5mxNWHk0QvEC6qMu2JQWHeott0ROYPkbXoNtuOOkzcsZhVaeb rjWH/WC5QhEeMPDc1qc0AmxVkOa937f2NkGtoEvhW6SMWvStHpefdOHo/ij106Re 7wxkcj0fjgn/zPmDltRbWSMyFZWJec5DvZ3AB4NYHnc2ycr8Z7HAG08rjZkdkIjQ zYGsCkUtrk4qShikKK3cSelW6hH1/FdM+bAo0rzt1frmTw1FLaFOsZZjOaVYekzi l0jxsb8FRBWyKBFqcagukjZwFy6D+7Q+masb0cXY03eZpEVrroA4bHiPkuZ22Ms/ 7ol/I5FvTyrj2R4zd70ziYVF3usO78t5HC4AIQmFl25TNcQdYQd8X28yh12iG6QN Pa0lh/EOr5idaT2+TErhzRepICnK1Nj9y0H5TZxYljLAhH9j0d/8+Iw88vzJnPga vek7unZ3BzkooLVIpfpkT8vC94MA0hoP849MVFQDtZgZhPMbjIkN91HrDiw9ktV2 SK9cuPndfrs5nW1WKu8F0cDziusbMHv4F51TPVRu/dFcIkspv+aLojAThgvcm42K 55LgvDgLjo7P3PUghiDXUoPZXvL19t5Bnq2/E47rlSTvvGssIu/onZO6BkxybAm6 BkHuchr8TGBWMg== =iCOr -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ... |
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abilis,tb10x-ictl.txt | ||
actions,owl-sirq.yaml | ||
al,alpine-msix.txt | ||
allwinner,sun4i-a10-ic.yaml | ||
allwinner,sun6i-a31-r-intc.yaml | ||
allwinner,sun7i-a20-sc-nmi.yaml | ||
amazon,al-fic.txt | ||
amlogic,meson-gpio-intc.txt | ||
apple,aic2.yaml | ||
apple,aic.yaml | ||
arm,gic-v3.yaml | ||
arm,gic.yaml | ||
arm,nvic.txt | ||
arm,versatile-fpga-irq.txt | ||
arm,vic.yaml | ||
aspeed,ast2xxx-scu-ic.txt | ||
aspeed,ast2400-i2c-ic.txt | ||
aspeed,ast2400-vic.txt | ||
atmel,aic.txt | ||
brcm,bcm2835-armctrl-ic.txt | ||
brcm,bcm2836-l1-intc.txt | ||
brcm,bcm6345-l1-intc.txt | ||
brcm,bcm7038-l1-intc.yaml | ||
brcm,bcm7120-l2-intc.yaml | ||
brcm,l2-intc.yaml | ||
cdns,xtensa-mx.txt | ||
cdns,xtensa-pic.txt | ||
cirrus,clps711x-intc.txt | ||
csky,apb-intc.txt | ||
csky,mpintc.txt | ||
digicolor-ic.txt | ||
ezchip,nps400-ic.txt | ||
faraday,ftintc010.txt | ||
fsl,intmux.yaml | ||
fsl,irqsteer.yaml | ||
fsl,ls-extirq.yaml | ||
fsl,ls-scfg-msi.txt | ||
fsl,mu-msi.yaml | ||
google,goldfish-pic.txt | ||
hisilicon,mbigen-v2.txt | ||
idt,32434-pic.yaml | ||
img,pdc-intc.txt | ||
ingenic,intc.yaml | ||
intel,ce4100-ioapic.txt | ||
intel,ixp4xx-interrupt.yaml | ||
interrupts.txt | ||
jcore,aic.txt | ||
kontron,sl28cpld-intc.yaml | ||
loongson,htpic.yaml | ||
loongson,htvec.yaml | ||
loongson,liointc.yaml | ||
loongson,ls1x-intc.txt | ||
loongson,pch-msi.yaml | ||
loongson,pch-pic.yaml | ||
lsi,zevio-intc.txt | ||
marvell,armada-8k-pic.txt | ||
marvell,armada-370-xp-mpic.txt | ||
marvell,gicp.txt | ||
marvell,icu.txt | ||
marvell,odmi-controller.txt | ||
marvell,orion-intc.txt | ||
marvell,sei.txt | ||
mediatek,cirq.txt | ||
mediatek,sysirq.txt | ||
microchip,eic.yaml | ||
microchip,pic32-evic.txt | ||
mrvl,intc.yaml | ||
mscc,ocelot-icpu-intr.yaml | ||
msi-controller.yaml | ||
msi.txt | ||
mstar,mst-intc.yaml | ||
mti,cpu-interrupt-controller.yaml | ||
mti,gic.yaml | ||
nuvoton,wpcm450-aic.yaml | ||
nvidia,tegra20-ictlr.txt | ||
nxp,lpc3220-mic.txt | ||
open-pic.txt | ||
opencores,or1k-pic.txt | ||
openrisc,ompic.txt | ||
qca,ath79-cpu-intc.txt | ||
qca,ath79-misc-intc.txt | ||
qcom,mpm.yaml | ||
qcom,pdc.yaml | ||
rda,8810pl-intc.yaml | ||
realtek,rtl-intc.yaml | ||
renesas,intc-irqpin.yaml | ||
renesas,irqc.yaml | ||
renesas,rza1-irqc.yaml | ||
renesas,rzg2l-irqc.yaml | ||
riscv,cpu-intc.txt | ||
samsung,exynos4210-combiner.yaml | ||
samsung,s3c24xx-irq.txt | ||
sifive,plic-1.0.0.yaml | ||
snps,arc700-intc.txt | ||
snps,archs-idu-intc.txt | ||
snps,archs-intc.txt | ||
snps,dw-apb-ictl.txt | ||
socionext,synquacer-exiu.txt | ||
socionext,uniphier-aidet.yaml | ||
st,spear3xx-shirq.txt | ||
st,sti-irq-syscfg.txt | ||
st,stm32-exti.yaml | ||
sunplus,sp7021-intc.yaml | ||
technologic,ts4800.txt | ||
ti,cp-intc.txt | ||
ti,keystone-irq.txt | ||
ti,omap2-intc.txt | ||
ti,omap4-wugen-mpu | ||
ti,omap-intc-irq.txt | ||
ti,pruss-intc.yaml | ||
ti,sci-inta.yaml | ||
ti,sci-intr.yaml | ||
via,vt8500-intc.txt |