- Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers (Luca Weiss). - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner). - Fix CPPC driver's freq/performance conversions (Pierre Gondois). - Minor generic cleanups (Yury Norov). - Introduce opp-microwatt property to the OPP core, bindings, etc (Lukasz Luba). - Convert DT bindings to schema format and various related fixes (Yassine Oudjana). - Expose OPP's OF node in debugfs (Viresh Kumar). - Add Intel uncore frequency scaling documentation file to its MAINTAINERS entry (Srinivas Pandruvada). - Clean up the AMD P-state driver documentation (Jan Engelhardt). -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAmJDPHMSHHJqd0Byand5 c29ja2kubmV0AAoJEILEb/54YlRxjYYQAJfa7TO+VtoB+0tSKKT0iVI52HVPyvr5 BTlDgCKmpt9/mfwfsa+9+RJ0k78pT8zWMl27VL1fAkF9SXbY13kbFIVyfWDoigiK uAH8hoWHp50PvyZtLHoiIzp5hBl/CLer/66Ys/jo32B5ui2iA50hCJ6W5KIpynT2 yzZBsyGNfak78Y6S6TyeMHR+8ytmfpsuDGMmcs8DVb8Fn6tlcBIfskZcYrimp1Ss IoiDvRvcavY0kZ5tBuzgikSzR4SJ8bx0hPzKnV/n6HCe2CAIg9o5HHnqPT8Su1ar dqI/ghkO+5JvHL1oxlperCDjfXREuYbpx7IkatN8zR9/Xkho5iabW+Pn/E0ZN/e9 boLzAWaHsJxnJkhcwKzOWeYhsbzNuNY+n9LjHHiUH2kgMCUsvPBPIcV5LgUU8oeX 1TXvl36OI883rgymBmi6nBc7+v/lE8qAxFds4M5rsLR173rcSewpiov/uOPgzGhe JyerIpuOU5EWbvJDUCLLgHVLlK+ciu/98wiuWQCWwwiNZBZGEMbxA8Die/0Pq3T5 Nvhh96EDqF6QPACAKTHTSMFDmHC9J78guFvqBSI3XiGDSTlTC+l3twNOT3mU1kUz s9pEwWROBnSg5QsfB/logsjV4q6RcEdSaKSW3bCZ/lRO18/daHFoLH/NlQif626O Jsx3k+vgd2Hv =rsb/ -----END PGP SIGNATURE----- Merge tag 'pm-5.18-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull more power management updates from Rafael Wysocki: "These update ARM cpufreq drivers, the OPP (Operating Performance Points) library and the power management documentation. Specifics: - Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers (Luca Weiss). - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner). - Fix CPPC driver's freq/performance conversions (Pierre Gondois). - Minor generic cleanups (Yury Norov). - Introduce opp-microwatt property to the OPP core, bindings, etc (Lukasz Luba). - Convert DT bindings to schema format and various related fixes (Yassine Oudjana). - Expose OPP's OF node in debugfs (Viresh Kumar). - Add Intel uncore frequency scaling documentation file to its MAINTAINERS entry (Srinivas Pandruvada). - Clean up the AMD P-state driver documentation (Jan Engelhardt)" * tag 'pm-5.18-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (24 commits) Documentation: amd-pstate: grammar and sentence structure updates dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example Documentation: EM: Describe new registration method using DT OPP: Add support of "opp-microwatt" for EM registration PM: EM: add macro to set .active_power() callback conditionally OPP: Add "opp-microwatt" supporting code dt-bindings: opp: Add "opp-microwatt" entry in the OPP MAINTAINERS: Add additional file to uncore frequency control cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev cpufreq: qcom-hw: Add support for per-core-dcvs dt-bindings: power: avs: qcom,cpr: Convert to DT schema arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables arm64: dts: qcom: msm8996: Rename cluster OPP tables dt-bindings: opp: Convert qcom-nvmem-cpufreq to DT schema dt-bindings: opp: qcom-opp: Convert to DT schema arm64: dts: qcom: msm8996-mtp: Add msm8996 compatible dt-bindings: arm: qcom: Add msm8996 and apq8096 compatibles opp: Expose of-node's name in debugfs cpufreq: CPPC: Fix performance/frequency conversion ...
80 lines
2.9 KiB
YAML
80 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic performance domains
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maintainers:
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- Sudeep Holla <sudeep.holla@arm.com>
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description: |+
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This binding is intended for performance management of groups of devices or
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CPUs that run in the same performance domain. Performance domains must not
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be confused with power domains. A performance domain is defined by a set
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of devices that always have to run at the same performance level. For a given
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performance domain, there is a single point of control that affects all the
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devices in the domain, making it impossible to set the performance level of
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an individual device in the domain independently from other devices in
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that domain. For example, a set of CPUs that share a voltage domain, and
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have a common frequency control, is said to be in the same performance
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domain.
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This device tree binding can be used to bind performance domain consumer
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devices with their performance domains provided by performance domain
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providers. A performance domain provider can be represented by any node in
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the device tree and can provide one or more performance domains. A consumer
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node can refer to the provider by a phandle and a set of phandle arguments
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(so called performance domain specifiers) of length specified by the
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\#performance-domain-cells property in the performance domain provider node.
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select: true
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properties:
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"#performance-domain-cells":
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description:
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Number of cells in a performance domain specifier. Typically 0 for nodes
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representing a single performance domain and 1 for nodes providing
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multiple performance domains (e.g. performance controllers), but can be
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any value as specified by device tree binding documentation of particular
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provider.
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enum: [ 0, 1 ]
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performance-domains:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description:
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A phandle and performance domain specifier as defined by bindings of the
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performance controller/provider specified by phandle.
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additionalProperties: true
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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performance: performance-controller@11bc00 {
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compatible = "mediatek,cpufreq-hw";
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reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
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#performance-domain-cells = <1>;
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};
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};
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// The node above defines a performance controller that is a performance
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// domain provider and expects one cell as its phandle argument.
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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performance-domains = <&performance 1>;
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};
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};
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