forked from Minki/linux
9a936d6c3d
Correct big-endian accesses to the CBUS UART, a Malta on-board discrete
TI16C550C part wired directly to the system controller's device bus, and
do not use byte swapping with the 32-bit accesses to the device.
The CBUS is used for devices such as the boot flash memory needed early
on in system bootstrap even before PCI has been initialised. Therefore
it uses the system controller's device bus, which follows the endianness
set with the CPU, which means no byte-swapping is ever required for data
accesses to CBUS, unlike with PCI.
The CBUS UART uses the UPIO_MEM32 access method, that is the `readl' and
`writel' MMIO accessors, which on the MIPS platform imply byte-swapping
with PCI systems. Consequently the wrong byte lane is accessed with the
big-endian configuration and the UART is not correctly accessed.
As it happens the UPIO_MEM32BE access method makes use of the `ioread32'
and `iowrite32' MMIO accessors, which still use `readl' and `writel'
respectively, however they byte-swap data passed, effectively cancelling
swapping done with the accessors themselves and making it suitable for
the CBUS UART.
Make the CBUS UART switch between UPIO_MEM32 and UPIO_MEM32BE then,
based on the endianness selected. With this change in place the device
is correctly recognised with big-endian Malta at boot, along with the
Super I/O devices behind PCI:
Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
printk: console [ttyS0] disabled
serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
printk: console [ttyS0] enabled
printk: bootconsole [uart8250] disabled
serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20, base_baud = 230400) is a 16550A
Fixes: e7c4782f92 ("[MIPS] Put an end to <asm/serial.h>'s long and annyoing existence")
Cc: stable@vger.kernel.org # v2.6.23+
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2106260524430.37803@angie.orcam.me.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006, 07 MIPS Technologies, Inc.
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* written by Ralf Baechle (ralf@linux-mips.org)
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* written by Ralf Baechle <ralf@linux-mips.org>
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*
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* Copyright (C) 2008 Wind River Systems, Inc.
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* updated by Tiejun Chen <tiejun.chen@windriver.com>
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*
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* 1. Probe driver for the Malta's UART ports:
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*
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* o 2 ports in the SMC SuperIO
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* o 1 port in the CBUS UART, a discrete 16550 which normally is only used
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* for bringups.
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*
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* We don't use 8250_platform.c on Malta as it would result in the CBUS
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* UART becoming ttyS0.
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*
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* 2. Register RTC-CMOS platform device on Malta.
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*/
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#include <linux/init.h>
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#include <linux/serial_8250.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <asm/mips-boards/maltaint.h>
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#define SMC_PORT(base, int) \
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{ \
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.iobase = base, \
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.irq = int, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | \
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UPF_MAGIC_MULTIPLIER, \
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.regshift = 0, \
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}
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#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
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static struct plat_serial8250_port uart8250_data[] = {
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SMC_PORT(0x3F8, 4),
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SMC_PORT(0x2F8, 3),
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#ifndef CONFIG_MIPS_CMP
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{
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.mapbase = 0x1f000900, /* The CBUS UART */
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.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
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.uartclk = 3686400, /* Twice the usual clk! */
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.iotype = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) ?
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UPIO_MEM32BE : UPIO_MEM32,
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.flags = CBUS_UART_FLAGS,
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.regshift = 3,
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},
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#endif
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{ },
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};
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static struct platform_device malta_uart8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = uart8250_data,
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},
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};
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static struct platform_device *malta_devices[] __initdata = {
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&malta_uart8250_device,
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};
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static int __init malta_add_devices(void)
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{
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return platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
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}
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device_initcall(malta_add_devices);
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