/* * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC * * Copyright (C) 2014 Atmel, * 2014 Nicolas Ferre * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" #include #include #include #include #include / { model = "Atmel SAMA5D4 family SoC"; compatible = "atmel,sama5d4"; interrupt-parent = <&aic>; aliases { serial0 = &usart3; serial1 = &usart4; serial2 = &usart2; gpio0 = &pioA; gpio1 = &pioB; gpio2 = &pioC; gpio3 = &pioD; gpio4 = &pioE; ssc0 = &ssc0; ssc1 = &ssc1; tcb0 = &tcb0; tcb1 = &tcb1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0>; next-level-cache = <&L2>; }; }; memory { reg = <0x20000000 0x20000000>; }; clocks { slow_xtal: slow_xtal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; main_xtal: main_xtal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; }; }; ns_sram: sram@00210000 { compatible = "mmio-sram"; reg = <0x00210000 0x10000>; }; ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; usb0: gadget@00400000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,at91sam9rl-udc"; reg = <0x00400000 0x100000 0xfc02c000 0x4000>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; clocks = <&udphs_clk>, <&utmi>; clock-names = "pclk", "hclk"; status = "disabled"; ep0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; ep1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; atmel,can-isoc; }; ep2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; atmel,can-isoc; }; ep3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; atmel,can-isoc; }; ep4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; atmel,can-isoc; }; ep5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; atmel,can-isoc; }; ep6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; atmel,can-isoc; }; ep7 { reg = <7>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; atmel,can-isoc; }; ep8 { reg = <8>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep9 { reg = <9>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep10 { reg = <10>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep11 { reg = <11>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep12 { reg = <12>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep13 { reg = <13>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep14 { reg = <14>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; ep15 { reg = <15>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; }; usb1: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; usb2: ehci@00600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; clocks = <&usb>, <&uhphs_clk>, <&uhpck>; clock-names = "usb_clk", "ehci_clk", "uhpck"; status = "disabled"; }; L2: cache-controller@00a00000 { compatible = "arm,pl310-cache"; reg = <0x00a00000 0x1000>; interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; cache-unified; cache-level = <2>; }; nand0: nand@80000000 { compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; #address-cells = <1>; #size-cells = <1>; ranges; reg = < 0x80000000 0x08000000 /* EBI CS3 */ 0xfc05c070 0x00000490 /* SMC PMECC regs */ 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ >; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; status = "disabled"; nfc@90000000 { compatible = "atmel,sama5d3-nfc"; #address-cells = <1>; #size-cells = <1>; reg = < 0x90000000 0x10000000 /* NFC Command Registers */ 0xfc05c000 0x00000070 /* NFC HSMC regs */ 0x00100000 0x00100000 /* NFC SRAM banks */ >; clocks = <&hsmc_clk>; atmel,write-by-sram; }; }; apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; dma1: dma-controller@f0004000 { compatible = "atmel,sama5d4-dma"; reg = <0xf0004000 0x200>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&dma1_clk>; clock-names = "dma_clk"; }; ramc0: ramc@f0010000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf0010000 0x200>; clocks = <&ddrck>, <&mpddr_clk>; clock-names = "ddrck", "mpddr"; }; dma0: dma-controller@f0014000 { compatible = "atmel,sama5d4-dma"; reg = <0xf0014000 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&dma0_clk>; clock-names = "dma_clk"; }; pmc: pmc@f0018000 { compatible = "atmel,sama5d3-pmc"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; main_rc_osc: main_rc_osc { compatible = "atmel,at91sam9x5-clk-main-rc-osc"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clock-frequency = <12000000>; clock-accuracy = <100000000>; }; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clocks = <&main_xtal>; }; main: mainck { compatible = "atmel,at91sam9x5-clk-main"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clocks = <&main_rc_osc &main_osc>; }; plla: pllack { compatible = "atmel,sama5d3-clk-pll"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clocks = <&main>; reg = <0>; atmel,clk-input-range = <12000000 12000000>; #atmel,pll-clk-output-range-cells = <4>; atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; }; plladiv: plladivck { compatible = "atmel,at91sam9x5-clk-plldiv"; #clock-cells = <0>; clocks = <&plla>; }; utmi: utmick { compatible = "atmel,at91sam9x5-clk-utmi"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clocks = <&main>; }; mck: masterck { compatible = "atmel,at91sam9x5-clk-master"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <125000000 177000000>; atmel,clk-divisors = <1 2 4 3>; }; h32ck: h32mxck { #clock-cells = <0>; compatible = "atmel,sama5d4-clk-h32mx"; clocks = <&mck>; }; usb: usbck { compatible = "atmel,at91sam9x5-clk-usb"; #clock-cells = <0>; clocks = <&plladiv>, <&utmi>; }; prog: progck { compatible = "atmel,at91sam9x5-clk-programmable"; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; prog0: prog0 { #clock-cells = <0>; reg = <0>; interrupts = ; }; prog1: prog1 { #clock-cells = <0>; reg = <1>; interrupts = ; }; prog2: prog2 { #clock-cells = <0>; reg = <2>; interrupts = ; }; }; smd: smdclk { compatible = "atmel,at91sam9x5-clk-smd"; #clock-cells = <0>; clocks = <&plladiv>, <&utmi>; }; systemck { compatible = "atmel,at91rm9200-clk-system"; #address-cells = <1>; #size-cells = <0>; ddrck: ddrck { #clock-cells = <0>; reg = <2>; clocks = <&mck>; }; lcdck: lcdck { #clock-cells = <0>; reg = <4>; clocks = <&smd>; }; smdck: smdck { #clock-cells = <0>; reg = <4>; clocks = <&smd>; }; uhpck: uhpck { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; udpck: udpck { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; pck0: pck0 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; pck1: pck1 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; }; pck2: pck2 { #clock-cells = <0>; reg = <10>; clocks = <&prog2>; }; }; periph32ck { compatible = "atmel,at91sam9x5-clk-peripheral"; #address-cells = <1>; #size-cells = <0>; clocks = <&h32ck>; pioD_clk: pioD_clk { #clock-cells = <0>; reg = <5>; }; usart0_clk: usart0_clk { #clock-cells = <0>; reg = <6>; }; usart1_clk: usart1_clk { #clock-cells = <0>; reg = <7>; }; icm_clk: icm_clk { #clock-cells = <0>; reg = <9>; }; aes_clk: aes_clk { #clock-cells = <0>; reg = <12>; }; tdes_clk: tdes_clk { #clock-cells = <0>; reg = <14>; }; sha_clk: sha_clk { #clock-cells = <0>; reg = <15>; }; matrix1_clk: matrix1_clk { #clock-cells = <0>; reg = <17>; }; hsmc_clk: hsmc_clk { #clock-cells = <0>; reg = <22>; }; pioA_clk: pioA_clk { #clock-cells = <0>; reg = <23>; }; pioB_clk: pioB_clk { #clock-cells = <0>; reg = <24>; }; pioC_clk: pioC_clk { #clock-cells = <0>; reg = <25>; }; pioE_clk: pioE_clk { #clock-cells = <0>; reg = <26>; }; uart0_clk: uart0_clk { #clock-cells = <0>; reg = <27>; }; uart1_clk: uart1_clk { #clock-cells = <0>; reg = <28>; }; usart2_clk: usart2_clk { #clock-cells = <0>; reg = <29>; }; usart3_clk: usart3_clk { #clock-cells = <0>; reg = <30>; }; usart4_clk: usart4_clk { #clock-cells = <0>; reg = <31>; }; twi0_clk: twi0_clk { reg = <32>; #clock-cells = <0>; }; twi1_clk: twi1_clk { #clock-cells = <0>; reg = <33>; }; twi2_clk: twi2_clk { #clock-cells = <0>; reg = <34>; }; mci0_clk: mci0_clk { #clock-cells = <0>; reg = <35>; }; mci1_clk: mci1_clk { #clock-cells = <0>; reg = <36>; }; spi0_clk: spi0_clk { #clock-cells = <0>; reg = <37>; }; spi1_clk: spi1_clk { #clock-cells = <0>; reg = <38>; }; spi2_clk: spi2_clk { #clock-cells = <0>; reg = <39>; }; tcb0_clk: tcb0_clk { #clock-cells = <0>; reg = <40>; }; tcb1_clk: tcb1_clk { #clock-cells = <0>; reg = <41>; }; tcb2_clk: tcb2_clk { #clock-cells = <0>; reg = <42>; }; pwm_clk: pwm_clk { #clock-cells = <0>; reg = <43>; }; adc_clk: adc_clk { #clock-cells = <0>; reg = <44>; }; dbgu_clk: dbgu_clk { #clock-cells = <0>; reg = <45>; }; uhphs_clk: uhphs_clk { #clock-cells = <0>; reg = <46>; }; udphs_clk: udphs_clk { #clock-cells = <0>; reg = <47>; }; ssc0_clk: ssc0_clk { #clock-cells = <0>; reg = <48>; }; ssc1_clk: ssc1_clk { #clock-cells = <0>; reg = <49>; }; trng_clk: trng_clk { #clock-cells = <0>; reg = <53>; }; macb0_clk: macb0_clk { #clock-cells = <0>; reg = <54>; }; macb1_clk: macb1_clk { #clock-cells = <0>; reg = <55>; }; fuse_clk: fuse_clk { #clock-cells = <0>; reg = <57>; }; securam_clk: securam_clk { #clock-cells = <0>; reg = <59>; }; smd_clk: smd_clk { #clock-cells = <0>; reg = <61>; }; twi3_clk: twi3_clk { #clock-cells = <0>; reg = <62>; }; catb_clk: catb_clk { #clock-cells = <0>; reg = <63>; }; }; periph64ck { compatible = "atmel,at91sam9x5-clk-peripheral"; #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; dma0_clk: dma0_clk { #clock-cells = <0>; reg = <8>; }; cpkcc_clk: cpkcc_clk { #clock-cells = <0>; reg = <10>; }; aesb_clk: aesb_clk { #clock-cells = <0>; reg = <13>; }; mpddr_clk: mpddr_clk { #clock-cells = <0>; reg = <16>; }; matrix0_clk: matrix0_clk { #clock-cells = <0>; reg = <18>; }; vdec_clk: vdec_clk { #clock-cells = <0>; reg = <19>; }; dma1_clk: dma1_clk { #clock-cells = <0>; reg = <50>; }; lcd_clk: lcd_clk { #clock-cells = <0>; reg = <51>; }; isi_clk: isi_clk { #clock-cells = <0>; reg = <52>; }; }; }; mmc0: mmc@f8000000 { compatible = "atmel,hsmci"; reg = <0xf8000000 0x600>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>; dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci0_clk>; clock-names = "mci_clk"; }; ssc0: ssc@f8008000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf8008000 0x4000>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(26))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(27))>; dma-names = "tx", "rx"; clocks = <&ssc0_clk>; clock-names = "pclk"; status = "disabled"; }; spi0: spi@f8010000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf8010000 0x100>; interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&spi0_clk>; clock-names = "spi_clk"; status = "disabled"; }; i2c0: i2c@f8014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x4000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi0_clk>; status = "disabled"; }; i2c1: i2c@f8018000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8018000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(4)>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(5)>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi1_clk>; status = "disabled"; }; tcb0: timer@f801c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf801c000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb0_clk>; clock-names = "t0_clk"; }; macb0: ethernet@f8020000 { compatible = "atmel,sama5d4-gem"; reg = <0xf8020000 0x100>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; #address-cells = <1>; #size-cells = <0>; clocks = <&macb0_clk>, <&macb0_clk>; clock-names = "hclk", "pclk"; status = "disabled"; }; i2c2: i2c@f8024000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8024000 0x4000>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi2_clk>; status = "disabled"; }; sfr: sfr@f8028000 { compatible = "atmel,sama5d4-sfr", "syscon"; reg = <0xf8028000 0x60>; }; mmc1: mmc@fc000000 { compatible = "atmel,hsmci"; reg = <0xfc000000 0x600>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci1_clk>; clock-names = "mci_clk"; }; usart2: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; clocks = <&usart2_clk>; clock-names = "usart"; status = "disabled"; }; usart3: serial@fc00c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; clocks = <&usart3_clk>; clock-names = "usart"; status = "disabled"; }; usart4: serial@fc010000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc010000 0x100>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart4>; clocks = <&usart4_clk>; clock-names = "usart"; status = "disabled"; }; ssc1: ssc@fc014000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xfc014000 0x4000>; interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(28))>, <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(29))>; dma-names = "tx", "rx"; clocks = <&ssc1_clk>; clock-names = "pclk"; status = "disabled"; }; tcb1: timer@fc020000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb1_clk>; clock-names = "t0_clk"; }; adc0: adc@fc034000 { compatible = "atmel,at91sam9x5-adc"; reg = <0xfc034000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = < /* external trigger is conflict with USBA_VBUS */ &pinctrl_adc0_ad0 &pinctrl_adc0_ad1 &pinctrl_adc0_ad2 &pinctrl_adc0_ad3 &pinctrl_adc0_ad4 >; clocks = <&adc_clk>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0x01f>; atmel,adc-startup-time = <40>; atmel,adc-use-external; atmel,adc-vref = <3000>; atmel,adc-res = <8 10>; atmel,adc-sample-hold-time = <11>; atmel,adc-res-names = "lowres", "highres"; atmel,adc-ts-pressure-threshold = <10000>; status = "disabled"; trigger@0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; trigger@1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; trigger@2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; trigger@3 { trigger-name = "continuous"; trigger-value = <0x6>; }; }; aes@fc044000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xfc044000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(41)>, <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(40)>; dma-names = "tx", "rx"; clocks = <&aes_clk>; clock-names = "aes_clk"; status = "disabled"; }; tdes@fc04c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc04c000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(42)>, <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(43)>; dma-names = "tx", "rx"; clocks = <&tdes_clk>; clock-names = "tdes_clk"; status = "disabled"; }; sha@fc050000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xfc050000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(44)>; dma-names = "tx"; clocks = <&sha_clk>; clock-names = "sha_clk"; status = "disabled"; }; rstc@fc068600 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; }; shdwc@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; }; pit: timer@fc068630 { compatible = "atmel,at91sam9260-pit"; reg = <0xfc068630 0x10>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; clocks = <&h32ck>; }; watchdog@fc068640 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfc068640 0x10>; status = "disabled"; }; sckc@fc068650 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfc068650 0x4>; slow_rc_osc: slow_rc_osc { compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; #clock-cells = <0>; clock-frequency = <32768>; clock-accuracy = <250000000>; atmel,startup-time-usec = <75>; }; slow_osc: slow_osc { compatible = "atmel,at91sam9x5-clk-slow-osc"; #clock-cells = <0>; clocks = <&slow_xtal>; atmel,startup-time-usec = <1200000>; }; clk32k: slowck { compatible = "atmel,at91sam9x5-clk-slow"; #clock-cells = <0>; clocks = <&slow_rc_osc &slow_osc>; }; }; rtc@fc0686b0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfc0686b0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; dbgu: serial@fc069000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc069000 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&dbgu_clk>; clock-names = "usart"; status = "disabled"; }; pinctrl@fc06a000 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfc06a000 0xfc06a000 0x4000>; /* WARNING: revisit as pin spec has changed */ atmel,mux-mask = < /* A B C */ 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ 0x00000000 0x00000000 0x00000000 /* pioD */ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ >; pioA: gpio@fc06a000 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfc06a000 0x100>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioA_clk>; }; pioB: gpio@fc06b000 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfc06b000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioB_clk>; }; pioC: gpio@fc06c000 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfc06c000 0x100>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioC_clk>; }; pioD: gpio@fc068000 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfc068000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioD_clk>; status = "disabled"; }; pioE: gpio@fc06d000 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfc06d000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioE_clk>; }; /* pinctrl pin settings */ adc0 { pinctrl_adc0_adtrg: adc0_adtrg { atmel,pins = ; /* conflicts with USBA_VBUS */ }; pinctrl_adc0_ad0: adc0_ad0 { atmel,pins = ; }; pinctrl_adc0_ad1: adc0_ad1 { atmel,pins = ; }; pinctrl_adc0_ad2: adc0_ad2 { atmel,pins = ; }; pinctrl_adc0_ad3: adc0_ad3 { atmel,pins = ; }; pinctrl_adc0_ad4: adc0_ad4 { atmel,pins = ; }; }; dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = , /* conflicts with D14 and TDI */ ; /* conflicts with D15 and TDO */ }; }; i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = ; }; }; i2c1 { pinctrl_i2c1: i2c1-0 { atmel,pins = ; /* TWCK1, conflicts with UART0 TX and DIBN */ }; }; i2c2 { pinctrl_i2c2: i2c2-0 { atmel,pins = ; /* TWCK2, conflicts with RF0 */ }; }; macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = ; }; }; mmc0 { pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { atmel,pins = ; }; pinctrl_mmc0_dat1_3: mmc0_dat1_3 { atmel,pins = ; }; }; mmc1 { pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { atmel,pins = ; }; pinctrl_mmc1_dat1_3: mmc1_dat1_3 { atmel,pins = ; }; }; nand0 { pinctrl_nand: nand-0 { atmel,pins = ; /* PC12 periph A Data bit 7 */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = ; }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx { atmel,pins = ; /* TD0 */ }; pinctrl_ssc0_rx: ssc0_rx { atmel,pins = ; /* RD0 */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx { atmel,pins = ; /* TD1 */ }; pinctrl_ssc1_rx: ssc1_rx { atmel,pins = ; /* RD1 */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = ; }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = ; }; }; usart4 { pinctrl_usart4: usart4-0 { atmel,pins = ; }; pinctrl_usart4_rts: usart4_rts-0 { atmel,pins = ; /* conflicts with NWAIT, A19 */ }; pinctrl_usart4_cts: usart4_cts-0 { atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ }; }; }; aic: interrupt-controller@fc06e000 { #interrupt-cells = <3>; compatible = "atmel,sama5d4-aic"; interrupt-controller; reg = <0xfc06e000 0x200>; atmel,external-irqs = <56>; }; }; }; };