/* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "dra72x.dtsi" / { model = "TI DRA722"; compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1024 MB */ }; }; &dra7_pmx_core { i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ >; }; nand_default: nand_default { pinctrl-single,pins = < 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ >; }; }; &i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; tps65917: tps65917@58 { compatible = "ti,tps65917"; reg = <0x58>; interrupts = ; /* IRQ_SYS_1N */ interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <2>; ti,system-power-controller; tps65917_pmic { compatible = "ti,tps65917-pmic"; regulators { smps1_reg: smps1 { /* VDD_MPU */ regulator-name = "smps1"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps2_reg: smps2 { /* VDD_CORE */ regulator-name = "smps2"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1030000>; regulator-boot-on; regulator-always-on; }; smps3_reg: smps3 { /* VDD_GPU IVA DSPEVE */ regulator-name = "smps3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps4_reg: smps4 { /* VDDS1V8 */ regulator-name = "smps4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; smps5_reg: smps5 { /* VDD_DDR */ regulator-name = "smps5"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: ldo1 { /* LDO1_OUT --> SDIO */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; ldo2_reg: ldo2 { /* LDO2_OUT --> TP1017 (UNUSED) */ regulator-name = "ldo2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; ldo3_reg: ldo3 { /* VDDA_1V8_PHY */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo5_reg: ldo5 { /* VDDA_1V8_PLL */ regulator-name = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo4_reg: ldo4 { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldo4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; }; }; }; }; &uart1 { status = "okay"; }; &elm { status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_default>; ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: * SW5.1 (NAND_SELn) = ON (LOW) * SW5.9 (GPMC_WPN) = OFF (HIGH) */ reg = <0 0 4>; /* device IO registers */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <80>; gpmc,cs-wr-off-ns = <80>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <60>; gpmc,adv-wr-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <50>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <40>; gpmc,access-ns = <40>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <80>; gpmc,wr-cycle-ns = <80>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000c0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001c0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001e0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x0f600000>; }; }; };