/*
 * SAMSUNG EXYNOS5440 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

/include/ "skeleton.dtsi"

/ {
	compatible = "samsung,exynos5440";

	interrupt-parent = <&gic>;

	clock: clock-controller@0x160000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x1000>;
		#clock-cells = <1>;
	};

	gic:interrupt-controller@2E0000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg =	<0x2E1000 0x1000>,
			<0x2E2000 0x1000>,
			<0x2E4000 0x2000>,
			<0x2E6000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		cpu@2 {
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		cpu@3 {
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,cortex-a15-timer",
			     "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <50000000>;
	};

	serial@B0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xB0000 0x1000>;
		interrupts = <0 2 0>;
		clocks = <&clock 21>, <&clock 21>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial@C0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xC0000 0x1000>;
		interrupts = <0 3 0>;
		clocks = <&clock 21>, <&clock 21>;
		clock-names = "uart", "clk_uart_baud0";
	};

	spi {
		compatible = "samsung,exynos4210-spi";
		reg = <0xD0000 0x1000>;
		interrupts = <0 4 0>;
		tx-dma-channel = <&pdma0 5>; /* preliminary */
		rx-dma-channel = <&pdma0 4>; /* preliminary */
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 21>, <&clock 16>;
		clock-names = "spi", "spi_busclk0";
	};

	pinctrl {
		compatible = "samsung,exynos5440-pinctrl";
		reg = <0xE0000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#gpio-cells = <2>;

		fan: fan {
			samsung,exynos5440-pin-function = <1>;
		};

		hdd_led0: hdd_led0 {
			samsung,exynos5440-pin-function = <2>;
		};

		hdd_led1: hdd_led1 {
			samsung,exynos5440-pin-function = <3>;
		};

		uart1: uart1 {
			samsung,exynos5440-pin-function = <4>;
		};
	};

	i2c@F0000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0xF0000 0x1000>;
		interrupts = <0 5 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 21>;
		clock-names = "i2c";
	};

	i2c@100000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0x100000 0x1000>;
		interrupts = <0 6 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 21>;
		clock-names = "i2c";
	};

	watchdog {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x110000 0x1000>;
		interrupts = <0 1 0>;
		clocks = <&clock 21>;
		clock-names = "watchdog";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;

		pdma0: pdma@121A0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x120000 0x1000>;
			interrupts = <0 34 0>;
			clocks = <&clock 21>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};

		pdma1: pdma@121B0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x121000 0x1000>;
			interrupts = <0 35 0>;
			clocks = <&clock 21>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};
	};

	rtc {
		compatible = "samsung,s3c6410-rtc";
		reg = <0x130000 0x1000>;
		interrupts = <0 17 0>, <0 16 0>;
		clocks = <&clock 21>;
		clock-names = "rtc";
	};
};