Commit Graph

4515 Commits

Author SHA1 Message Date
Kees Cook
bebfef150e UBI: avoid workqueue format string leak
When building the name for the workqueue thread, make sure a format
string cannot leak in from the disk name.

Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-05-05 09:31:33 +03:00
Tanya Brokhman
3d21bb7667 UBI: fix ubi free PEBs count calculation
The ubi->free_count should be updated with every insert/remove to/from
the ubi->free list.

Signed-off-by: Tanya Brokhman <tlinder@codeaurora.org>
Reviewed-by: Dolev Raviv <draviv@codeaurora.org>
Acked-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-05-05 09:31:33 +03:00
Tanya Brokhman
87ed89d21e UBI: fix error path in __wl_get_peb
In case of an error (if there are not free PEB's for example),
__wl_get_peb will return a negative value. In order to prevent access
violation we need to test the returned value prior to using it later on.

Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Reviewed-by: Dolev Raviv <draviv@codeaurora.org>
Acked-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-05-05 09:31:33 +03:00
Murali Karicheri
28c015a9da mtd: davinci-nand: disable subpage write for keystone-nand
Sub page write doesn't work because of hw issue in controller found on
Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which
don't seems to have any issue. So add "ti,keysone-nand" compatible
to nand driver in order to set NAND_NO_SUBPAGE_WRITE option.

Cc: Warner Losh <imp@bsdimp.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-30 15:26:49 -07:00
Masahiro Yamada
35fc51956b mtd: nand: fix a typo in a comment line
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-29 12:12:21 -07:00
Viresh Kumar
9cc236827f Shiraz has moved
shiraz.hashim@st.com email-id doesn't exist anymore as he has left the
company.  Replace ST's id with shiraz.linux.kernel@gmail.com.

It also updates .mailmap file to fix address for 'git shortlog'.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-18 16:40:08 -07:00
Akinobu Mita
be54f8f1c7 mtd: mtd_oobtest: generate consistent data for verification
mtd_oobtest writes OOB, read it back and verify.  The verification is
not correctly done if oobsize is not multiple of 4.  Although the data
to be written and the data to be compared are generated by several
prandom_byte_state() calls starting with the same seed, these two are
generated with the different size and different number of calls.

Due to the implementation of prandom_byte_state() if the size on each
call is not multiple of 4, the resulting data is not always same.

This fixes it by just calling prandom_byte_state() once and using
correct range instead of calling it multiple times for each.

Reported-by: George Cherian <george.cherian@ti.com>
Reported-by: Lothar Waßmann <LW@KARO-electronics.de>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Cc: George Cherian <george.cherian@ti.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-17 22:22:03 -07:00
Brian Norris
d66d3519c6 Merge branch 'spinor'
Addition of the spi-nor framework, plus updates to the ST SPI FSM
driver.
2014-04-16 22:06:09 -07:00
Brian Norris
dc002f99f3 mtd: st_spi_fsm: only build for ARM
COMPILE_TEST allows us to build this driver on other arch'es. But not
all arch'es have the right I/O accessors -- particularly, x86 is missing
readsl() and writesl().

So just restrict this driver to ARCH_STI. It's still buildable for a
multiplatform ARM kernel, so it can get decent compile coverage.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
2014-04-16 21:59:29 -07:00
Brian Norris
38e2eee9ab mtd: st_spi_fsm: correct type issues
Compile-testing for a 64-bit arch uncovers several bad casts:

    In file included from include/linux/linkage.h:4:0,
                     from include/linux/kernel.h:6,
                     from drivers/mtd/devices/st_spi_fsm.c:15:
    drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_read_fifo’:
    drivers/mtd/devices/st_spi_fsm.c:758:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
    ...

Use uintptr_t instead of uint32_t, since it's guaranteed to be
pointer-sized.

We also see this warning, if size_t is not 32 bits wide:

    In file included from drivers/mtd/devices/st_spi_fsm.c:15:0:
    drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_mtd_write’:
    include/linux/kernel.h:712:17: warning: comparison of distinct pointer types lacks a cast [enabled by default]
      (void) (&_min1 == &_min2);  \
                     ^
    drivers/mtd/devices/st_spi_fsm.c:1704:11: note: in expansion of macro ‘min’
       bytes = min(FLASH_PAGESIZE - page_offs, len);
               ^

Just use min_t() to force the type conversion, since we don't really
want to upgrade 'page_offs' and 'bytes' to size_t; they only should be
handling <= 256 byte offsets.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
2014-04-16 21:59:23 -07:00
Brian Norris
a965d04c97 mtd: fsl-quadspi: fix __iomem annotations
This corrects some sparse warnings:

   drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    expected void *[noderef] <asn:2>base [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    got void [noderef] <asn:2>*iobase [sparse]
   (etc.)

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-16 02:14:06 -07:00
Huang Shijie
6189cccbe8 mtd: gpmi: add gpmi_devdata{} to simplify the code
More and more chips use the GPMI controller, but these chips may use different
version of the IPs for GPMI and BCH. Different IPs have
 different features, such as the BCH's maximum ECC strength:

     imx23/imx28 -- the BCH's maximum ECC strength is 20
     imx6q       -- the BCH's maximum ECC strength is 40
     imx6sx      -- the BCH's maximum ECC strength is 62

This patch does the following things:

  [1] add a new data structure, gpmi_devdata{}, to store the information for
      each IP. Besides the IP version, we store the following information:
         <1> BCH's maximum ECC strength.
         <2> the maximum chain delay in ns used by the EDO mode.

      but we may add more information in future.

  [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids.

  [3] simplify the code by using the ECC strength from gpmi_devdata, such as
      gpmi_check_ecc() and legacy_set_geometry();

  [4] use the maximum chain delay to initialize the EDO mode,
      see gpmi_compute_edo_timing().

  [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-16 00:46:55 -07:00
Raphaël Poggi
85a3bd978e mtd: nand: add line feed to pr_err
Add line feed to pr_err.

Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-16 00:18:26 -07:00
Murali Karicheri
b4a812825d mtd: davinci-nand: disable subpage write for keystone-nand
Sub page write doesn't work because of hw issue in controller found on
Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which
don't seems to have any issue. So add "ti,keysone-nand" compatible
to nand driver in order to set NAND_NO_SUBPAGE_WRITE option.

Cc: Warner Losh <imp@bsdimp.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15 23:56:24 -07:00
Roman Peniaev
566c0d6a74 mtd: mtd_blkdevs: handle REQ_FLUSH request and do explicit flush of writeback buffer
mtd_blkdevs is device with volatile cache (writeback buffer), so it should support
REQ_FLUSH to do explicit flush.

Without this patch 'sync' does not guarantee that writeback buffer will be flushed
on disk in case of power off, e.g.:

  $ cp some_file /mnt
  $ sync

  ### POWER OFF

In case of this sequence writeback buffer will not be flushed on disk.

This patch fixes this behaviour and explicitly reports to block layer that flush
requests are being supported.

Signed-off-by: Roman Peniaev <r.peniaev@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15 23:25:37 -07:00
Ron
47570bb1f5 mtd: nand: use the nand_read_subpage index everywhere
Now that the index variable is correctly set earlier in this function
we can use it in other places that compute the same thing too.

Signed-off-by: Ron Lee <ron@debian.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15 23:25:36 -07:00
Christian Engelmayer
9fd6c6c18c mtd: nand: omap: fix compile warning on ‘erased_sector_bitflips’
Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4
in omap_calculate_ecc_bch) introduced minor compile warning
"‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when
compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function
erased_sector_bitflips() into the same ifdef section as the only caller.

Signed-off-by: Christian Engelmayer <cengelma@gmx.at>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15 23:20:30 -07:00
Jens Axboe
b4f42e2831 block: remove struct request buffer member
This was used in the olden days, back when onions were proper
yellow. Basically it mapped to the current buffer to be
transferred. With highmem being added more than a decade ago,
most drivers map pages out of a bio, and rq->buffer isn't
pointing at anything valid.

Convert old style drivers to just use bio_data().

For the discard payload use case, just reference the page
in the bio.

Signed-off-by: Jens Axboe <axboe@fb.com>
2014-04-15 14:03:02 -06:00
Brian Norris
8ac326fce9 mtd: spi-nor: allow to be built as module
There's no reason this can't be a module. Also, give SPI-NOR its own
submenu.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-14 11:23:02 -07:00
Brian Norris
6c8e1b33aa mtd: st_spi_fsm: begin using spi-nor.h opcodes
Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h.
Let's begin to unify them.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-14 11:23:01 -07:00
Brian Norris
92d3af9ac3 mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_*
Begin to unify the differences between serial_flash_cmds.h and
spi-nor.h.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-14 11:23:01 -07:00
Brian Norris
a402191e9b mtd: st_spi_fsm: kill duplicate CMD definitions
These are also in serial_flash_cmds.h. (FWIW, I didn't know the C
preprocessor allowed redefinitions without warning like this.)

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-14 11:23:01 -07:00
Brian Norris
8607bd4272 mtd: st_spi_fsm: fixup Kconfig dependency
I hear that this driver should depend on ARCH_STI, and that "SH" is not
actually a real symbol. At the same time, let's allow compile-testing on
other ARCH'es.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-14 11:23:01 -07:00
Brian Norris
e43b20619b mtd: spi-nor: shorten Kconfig naming
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-14 11:23:01 -07:00
Brian Norris
58b89a1f4c mtd: spi-nor: unify read opcode variants with ST SPI FSM
serial_flash_cmds.h defines our opcodes a little differently. Let's
borrow its naming, since it's borrowed from the SFDP standard, and it's
more extensible.

This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode
listing.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-14 11:23:00 -07:00
Brian Norris
b02e7f3ef0 mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*
Qualify these with a better namespace, and prepare them for use in more
drivers.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-04-14 11:23:00 -07:00
Huang Shijie
8eabdd1ec1 mtd: spi-nor: add the copyright information
Add the copyright information for spi-nor.c and spi-nor.h.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:23:00 -07:00
Angus Clark
6b6d37377c mtd: st_spi_fsm: Add support for Macronix MX25L3255E
This patch adds support for the Macronix MX25L3255E device.  Unlike the other
Macronix devices we have seen, this device supports WRITE_1_4_4 at reasonable
frequencies.  Rather than masking out WRITE_1_4_4 support altogether, we now
rely on the table parameters to indicate whether or not WRITE_1_4_4 should be
used.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:23:00 -07:00
Angus Clark
85bdcf6b25 mtd: st_spi_fsm: Add Spansion S25FL032P to device table
Add Spansion S25FL032P to the list of known devices.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:23:00 -07:00
Angus Clark
5d0bddab39 mtd: st_spi_fsm: Refactor status register operations
This patch refactors the fsm_read_status() and fsm_write_status() code to
support 1 or 2 byte operations, with a specified command.  This allows us to
remove device/register specific code, such as the N25Q fsm_wrvcr() function.

The 'QE' configuration code is updated accordingly, with minor tweaks to ensure
the register values are only written if actually required.  One notable change
in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect
to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only
used for write operations.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Angus Clark
cc6668637e mtd: st_spi_fsm: Update Macronix 'QE' configuration
Update the configuration of the Macronix 'QE' bit, such that
we only set or clear the bit if required.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Angus Clark
009e7e61b1 mtd: st_spi_fsm: Update Macronix 32-bit addressing support
Support for the Macronix 32-bit addressing scheme was originally developed using
the MX25L25635E device.  As is often the case, it was found that the presence of
a "WAIT" instruction was required for the "EN4B/EX4B" FSM Sequence to complete.
(It is known that the SPI FSM Controller makes certain undocumented assumptions
regarding what constitutes a valid sequence.)  However, further testing
suggested that a small delay was required after issuing the "EX4B" command;
without this delay, data corruptions were observed, consistent with the device
not being ready to retrieve data.  Although the issue was not fully understood,
the workaround of adding a small delay was implemented, while awaiting
clarification from Macronix.

The same behaviour has now been found with a second Macronix device, the
MX25L25655E.  However, with this device, it seems that the delay is also
required after the 'EN4B' commands.  This discovery has prompted us to revisit
the issue.

Although still not conclusive, further tests have suggested that the issue is
down to the SPI FSM Controller, rather than the Macronix devices.  Furthermore,
an alternative workaround has emerged which is to set the WAIT time to
0x00000001, rather then 0x00000000.  (Note, the WAIT instruction is used purely
for the purpose of achieving "sequence validity", rather than actually
implementing a delay!)

The issue is now being investigated by the Design and Validation teams.  In the
meantime, we implement the alternative workaround, which reduces the effective
delay from 1us to 1ns.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Angus Clark
5fa980691b mtd: st_spi_fsm: Add Macronix MX25L25655E device
Add Macronix MX25L25655E to the list of known devices.

Signed-off-by: Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Brian Norris
b61834b0d0 mtd: spi-nor: EXPORT symbols which could be used by module drivers
Fix errors like this:

    ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined!
    ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined!
    make[1]: *** [__modpost] Error 1
    make: *** [modules] Error 2

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Huang Shijie
e46ecda764 mtd: spi-nor: Add Freescale QuadSPI driver
(0) What is the QuadSPI controller?

    The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to
    one single or two external serial flash devices, each with up to 4
    bidirectional data lines.

(1) The QuadSPI controller is driven by the LUT(Look-up Table) registers.
    The LUT registers are a look-up-table for sequences of instructions.
    A valid sequence consists of four LUT registers.

(2) The definition of the LUT register shows below:

    ---------------------------------------------------
    | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
    ---------------------------------------------------

    There are several types of INSTRx, such as:
	CMD	: the SPI NOR command.
	ADDR	: the address for the SPI NOR command.
	DUMMY	: the dummy cycles needed by the SPI NOR command.
	....

    There are several types of PADx, such as:
	PAD1	: use a singe I/O line.
	PAD2	: use two I/O lines.
	PAD4	: use quad I/O lines.
	....

(3) Test this driver with the JFFS2 and UBIFS:

    For jffs2:
    -------------
	#flash_eraseall /dev/mtd0
	#mount -t jffs2 /dev/mtdblock0 tmp
	#bonnie++ -d tmp -u 0 -s 10 -r 5

    For ubifs:
    -------------
	#flash_eraseall /dev/mtd0
	#ubiattach /dev/ubi_ctrl -m 0
	#ubimkvol /dev/ubi0 -N test -m
	#mount -t ubifs ubi0:test tmp
	#bonnie++ -d tmp -u 0 -s 10 -r 5

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:59 -07:00
Huang Shijie
0d8c11c012 mtd: spi-nor: add a helper to find the spi_device_id
Add the spi_nor_match_id() to find the proper spi_device_id with the
NOR flash's name in the spi_nor_ids table.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:58 -07:00
Brian Norris
03e296f613 mtd: m25p80: use the SPI nor framework
Use the new SPI nor framework, and rewrite the m25p80:
 (0) remove all the NOR comands.
 (1) change the m25p->command to an array.
 (2) implement the necessary hooks, such as m25p80_read/m25p80_write.

Tested with the m25p32.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:58 -07:00
Huang Shijie
b199489d37 mtd: spi-nor: add the framework for SPI NOR
This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer.

Before this patch, the layer is like:

                   MTD
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	        SPI NOR chip

After this patch, the layer is like:
                   MTD
         ------------------------
                  spi-nor
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	       SPI NOR chip

With the spi-nor controller driver(Freescale Quadspi), it looks like:
                   MTD
         ------------------------
                  spi-nor
         ------------------------
                fsl-quadspi
         ------------------------
	       SPI NOR chip

New APIs:
   spi_nor_scan: used to scan a spi-nor flash.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased to include additional m25p_ids[] entry]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-14 11:22:58 -07:00
Linus Torvalds
c29aa153ef MTD updates for 3.15:
- A few SPI NOR ID definitions
  - Kill the NAND "max pagesize" restriction
  - Fix some x16 bus-width NAND support
  - Add NAND JEDEC parameter page support
  - DT bindings for NAND ECC
  - GPMI NAND updates (subpage reads)
  - More OMAP NAND refactoring
  - New STMicro SPI NOR driver (now in 40 patches!)
  - A few other random bugfixes
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Merge tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd

Pull MTD updates from Brian Norris:
 - A few SPI NOR ID definitions
 - Kill the NAND "max pagesize" restriction
 - Fix some x16 bus-width NAND support
 - Add NAND JEDEC parameter page support
 - DT bindings for NAND ECC
 - GPMI NAND updates (subpage reads)
 - More OMAP NAND refactoring
 - New STMicro SPI NOR driver (now in 40 patches!)
 - A few other random bugfixes

* tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd: (120 commits)
  Fix index regression in nand_read_subpage
  mtd: diskonchip: mem resource name is not optional
  mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH
  mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
  mtd: omap2: Use devm_ioremap_resource()
  mtd: denali_dt: Use devm_ioremap_resource()
  mtd: devices: elm: update DRIVER_NAME as "omap-elm"
  mtd: devices: elm: configure parallel channels based on ecc_steps
  mtd: devices: elm: clean elm_load_syndrome
  mtd: devices: elm: check for hardware engine's design constraints
  mtd: st_spi_fsm: Succinctly reorganise .remove()
  mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU
  mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"
  mtd: st_spi_fsm: Avoid duplicating MTD core code
  mtd: st_spi_fsm: Remove useless consts from function arguments
  mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions
  mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct
  mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back
  mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back
  mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back
  ...
2014-04-07 10:17:30 -07:00
Linus Torvalds
cbda94e039 ARM: SoC: driver changes
These changes are mostly for ARM specific device drivers that either
 don't have an upstream maintainer, or that had the maintainer ask
 us to pick up the changes to avoid conflicts. A large chunk of this
 are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from
 that, reset controllers for STi as well as a large rework of the
 Marvell Orion/EBU watchdog driver are notable.
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Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Arnd Bergmann:
 "These changes are mostly for ARM specific device drivers that either
  don't have an upstream maintainer, or that had the maintainer ask us
  to pick up the changes to avoid conflicts.

  A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
  shmobile), aside from that, reset controllers for STi as well as a
  large rework of the Marvell Orion/EBU watchdog driver are notable"

* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
  Revert "net: stmmac: Add SOCFPGA glue driver"
  ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
  ARM: STi: Add reset controller support to mach-sti Kconfig
  drivers: reset: stih416: add softreset controller
  drivers: reset: stih415: add softreset controller
  drivers: reset: Reset controller driver for STiH416
  drivers: reset: Reset controller driver for STiH415
  drivers: reset: STi SoC system configuration reset controller support
  dts: socfpga: Add sysmgr node so the gmac can use to reference
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  reset: Add optional resets and stubs
  ARM: shmobile: r7s72100: fix bus clock calculation
  Power: Reset: Generalize qnap-poweroff to work on Synology devices.
  dts: socfpga: Update clock entry to support multiple parents
  ARM: socfpga: Update socfpga_defconfig
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  net: stmmac: Add SOCFPGA glue driver
  watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
  drivers: cci: Export CCI PMU revision
  ...
2014-04-05 15:37:40 -07:00
Ron
4a4163cacc Fix index regression in nand_read_subpage
Commit 7351d3a5db added an index variable
as part of fixing checkpatch warnings, presumably as a tool to make some
long lines shorter, however it only set that index in the case of there
being no gaps in eccpos for the fragment being read.  Which means the
later step of filling ecccode from oob_poi will use the wrong indexing
into eccpos in that case.

This patch restores the behaviour that existed prior to that change.

Signed-off-by: Ron Lee <ron@debian.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-04 23:13:17 -07:00
Linus Torvalds
370d2662d5 This pull request includes the 'ubiblock' driver which provides R/O block
access to UBI volumes. It is useful for those who want to use squashfs on top
 of raw flash devices. UBI will provide bit-flip handling and wear-levelling in
 this case (e.g., if there are other UBI volumes with R/W UBIFS too).
 
 The driver is actually pretty small and it is part of the UBI kernel subsystem.
 Delivered by Ezequiel Garcia, along with a piece of documentation on the MTD
 web site and the user-space tool for creating and removing block devices.
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Merge tag 'upstream-3.15-rc1' of git://git.infradead.org/linux-ubifs

Pull ubifs updates from Artem Bityutskiy:
 "This pull request includes the 'ubiblock' driver which provides R/O
  block access to UBI volumes.  It is useful for those who want to use
  squashfs on top of raw flash devices.  UBI will provide bit-flip
  handling and wear-levelling in this case (e.g., if there are other UBI
  volumes with R/W UBIFS too).

  The driver is actually pretty small and it is part of the UBI kernel
  subsystem.  Delivered by Ezequiel Garcia, along with a piece of
  documentation on the MTD web site and the user-space tool for creating
  and removing block devices"

* tag 'upstream-3.15-rc1' of git://git.infradead.org/linux-ubifs:
  UBI: block: Remove __initdata from ubiblock_param_ops
  UBI: make UBI_IOCVOLCRBLK take a parameter for future usage
  UBI: rename block device ioctls
  UBI: block: Use ENOSYS as return value when CONFIG_UBIBLOCK=n
  UBI: block: Add CONFIG_BLOCK dependency
  UBI: block: Use 'u64' for the 64-bit dividend
  UBI: block: Mark init-only symbol as __initdata
  UBI: block: do not use term "attach"
  UBI: R/O block driver on top of UBI volumes
2014-04-04 15:35:38 -07:00
Linus Torvalds
675c354a95 Char/Misc driver patches for 3.15-rc1
Here's the big char/misc driver updates for 3.15-rc1.
 
 Lots of various things here, including the new mcb driver subsystem.
 
 All of these have been in linux-next for a while.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver patches from Greg KH:
 "Here's the big char/misc driver updates for 3.15-rc1.

  Lots of various things here, including the new mcb driver subsystem.

  All of these have been in linux-next for a while"

* tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (118 commits)
  extcon: Move OF helper function to extcon core and change function name
  extcon: of: Remove unnecessary function call by using the name of device_node
  extcon: gpio: Use SIMPLE_DEV_PM_OPS macro
  extcon: palmas: Use SIMPLE_DEV_PM_OPS macro
  mei: don't use deprecated DEFINE_PCI_DEVICE_TABLE macro
  mei: amthif: fix checkpatch error
  mei: client.h fix checkpatch errors
  mei: use cl_dbg where appropriate
  mei: fix Unnecessary space after function pointer name
  mei: report consistently copy_from/to_user failures
  mei: drop pr_fmt macros
  mei: make me hw headers private to me hw.
  mei: fix memory leak of pending write cb objects
  mei: me: do not reset when less than expected data is received
  drivers: mcb: Fix build error discovered by 0-day bot
  cs5535-mfgpt: Simplify dependencies
  spmi: pm: drop bus-level PM suspend/resume routines
  spmi: pmic_arb: make selectable on ARCH_QCOM
  Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle
  pch_phub: Report error writing MAC back to user
  ...
2014-04-01 16:13:21 -07:00
Sasha Levin
86e4bbc766 mtd: diskonchip: mem resource name is not optional
Passing a name to request_mem_region() isn't optional and can't just
be NULL. Passing NULL causes a NULL ptr deref later in the boot
process.

Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Tested-by: Alexander Shiyan <shc_work@mail.ru>
Cc: <stable@vger.kernel.org> # 3.14
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-31 18:43:22 -07:00
Erico Nunes
148256fa0b mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH
Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this
doesn't match the exact name of the configuration option.
This warning showed up once to me when I was starting to set up BCH. After
checking my .config file, it took a moment before realizing it is
CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-26 00:33:42 -07:00
Jingoo Han
00d09891eb mtd: omap2: Use devm_ioremap_resource()
Use devm_ioremap_resource() in order to make the code simpler,
and remove redundant return value check of platform_get_resource()
because the value is checked by devm_ioremap_resource(). Also,
'unsigned long mem_size' is removed from 'struct omap_nand_info',
because the 'mem_size' variable is not necessary anymore.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:21:15 -07:00
Jingoo Han
7995204e3c mtd: denali_dt: Use devm_ioremap_resource()
Use devm_ioremap_resource() in order to make the code
simpler, and remove redundant return value check of
platform_get_resource_byname() because the value is
checked by devm_ioremap_resource().

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:21:08 -07:00
Pekon Gupta
c7ea95a377 mtd: devices: elm: update DRIVER_NAME as "omap-elm"
use "omap-elm" as DRIVER_NAME

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:09:06 -07:00
Pekon Gupta
79f013518d mtd: devices: elm: configure parallel channels based on ecc_steps
ELM hardware can process up to maximum of 8 hannels in parallel for
ECC error detection. Currently the number of channels getting configured for
processing is static determined by macro ERROR_VECTOR_MAX. However, the actual
number of channels that need to be processed is the ECC step number.
This patch just avoids configuring extra unused channels.

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:09:02 -07:00
Pekon Gupta
ea0760244d mtd: devices: elm: clean elm_load_syndrome
This patch refactors elm_load_syndrome() to make it scalable for newer
ECC schemes by removing scheme specific macros (like ECC_BYTES*xx),
and instead using ECC control information passed during elm_config.

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:08:57 -07:00
Pekon Gupta
3f4eb14bdb mtd: devices: elm: check for hardware engine's design constraints
ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC
errors. This patch adds the following checks for ELM hardware engine:

 - ELM internal buffers are of 1K,
   so it cannot process data with ecc-step-size > 1K.

 - ELM engine can execute upto maximum of 8 threads in parallel,
   so in *page-mode* (when complete page is processed in single iteration),
   ELM cannot support ecc-steps > 8.

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25 23:08:52 -07:00
Richard Weinberger
d56030ac25 UBI: block: Remove __initdata from ubiblock_param_ops
You cannot mark these parameters as __initdata.
Otherwise the data is gone upon module exit.

Fixes:
[  172.045465] BUG: unable to handle kernel paging request at ffffffffa001db38
[  172.046020] IP: [<ffffffff81067aa4>] destroy_params+0x24/0x50

Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-03-21 19:37:03 +02:00
Rafael J. Wysocki
165f5fd04a Merge branches 'pm-qos', 'pm-domains' and 'pm-drivers'
* pm-qos:
  PM / QoS: Add type to dev_pm_qos_add_ancestor_request() arguments
  ACPI / LPSS: Support for device latency tolerance PM QoS
  ACPI / scan: Add bind/unbind callbacks to struct acpi_scan_handler
  PM / QoS: Introcuce latency tolerance device PM QoS type
  PM / QoS: Add no_constraints_value field to struct pm_qos_constraints
  PM / QoS: Rename device resume latency QoS items

* pm-domains:
  PM / domains: Turn latency warning into debug message

* pm-drivers:
  PM: Add pm_runtime_suspend|resume_force functions
  PM / runtime: Fetch runtime PM callbacks using a macro
2014-03-20 13:25:36 +01:00
Lee Jones
d9ba46d32c mtd: st_spi_fsm: Succinctly reorganise .remove()
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:56:53 -07:00
Lee Jones
ea7864bf44 mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:56:52 -07:00
Lee Jones
f1919cb852 mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:56:52 -07:00
Lee Jones
0419a203f8 mtd: st_spi_fsm: Avoid duplicating MTD core code
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:56:51 -07:00
Lee Jones
3f9d720a4d mtd: st_spi_fsm: Remove useless consts from function arguments
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
[Brian: tweaked a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:56:51 -07:00
Lee Jones
221cff13ca mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions
The old API expected a "partitions" property provided a phandle to a
separate partitions node, which itself contained yet more nodes each
representing one partition. The new API rids the requirement for the
superfluous intermediary partitions node. This patch provides the
added information required for automatic parsing by the core.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:22 -07:00
Lee Jones
e6b1bb4e18 mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct
Until now the dynamically configurable message sequences for read, write
and enable 32bit addressing have been global. Brian makes a good point
why this should not be the case. If there are ever two FSM's located on
the same platform, we could be potentially introducing a race condition
on "needlessly shared data".

Suggested-by: Brian Norris <computersforpeace@gmail.com>
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:21 -07:00
Lee Jones
cd7cac9ec3 mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:21 -07:00
Lee Jones
5343a12345 mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back
This patch allows us to prepare some of the message sequences which will
be required to talk to the  S25FLxxx family of Serial Flash devices. It
also allows us to do some required extra operations after any busy wait
failures.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:21 -07:00
Lee Jones
898180665f mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:21 -07:00
Lee Jones
150571b74a mtd: st_spi_fsm: Add the ability to write to FSM's status register
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:20 -07:00
Lee Jones
ac94dbcb67 mtd: st_spi_fsm: Add the ability to read the FSM's status
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:20 -07:00
Lee Jones
4a341fe758 mtd: st_spi_fsm: Erase partly or as a whole a Serial Flash device
When an erase is requested by userspace the MTD framework calls back
into the driver to conduct the actual command issue. Here we provide the
routines which do exactly that. We can choose to either do an entire chip
erase or by sector.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:20 -07:00
Lee Jones
176b437762 mtd: st_spi_fsm: Supply a busy wait for post-write status
When we write data to the Serial Flash chip we'll wait a predetermined
period of time before giving up. During that period of time we poll the
status register until completion.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:19 -07:00
Lee Jones
30ca64f9f9 mtd: st_spi_fsm: Write to Flash via the FSM FIFO
When we write data to the FIFO the FSM Controller subsequently writes
that data out to the Serial Flash chip.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:19 -07:00
Lee Jones
e514f10578 mtd: st_spi_fsm: Add the ability to read from a Serial Flash device
When a read is issued by userspace the MTD framework calls back into
the driver to conduct the actual command issue and data extraction.
Here we provide the routines which do exactly that.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:19 -07:00
Lee Jones
4eb3f0d8f7 mtd: st_spi_fsm: Prepare default sequences for read/write/erase
Most chips require a predefined set of FSM message sequences for read,
write and erase operations. This patch provides a way to set them up,
which it will do so if a chip specific initialisation routine isn't
been provided.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
218b870f90 mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-back
In the FSM driver we handle chip differences by providing the possibility
of calling back into a chip specific initialisation routine. In this patch
we provide one for the N25Qxxx series, which endeavours to setup things
like the read, write and erase sequences, as they differ from the
default. We also configure 32bit support and the amount of dummy cycles to
use.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
e85a619676 mtd: st_spi_fsm: Supply the N25Qxxx specific read configurations
The N25Qxxx Serial Flash devices required different sequence
configurations depending on whether they're running in 24bit (3Byte)
or 32bit (4Byte) mode. We provide those here.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
a37b2f5aee mtd: st_spi_fsm: Provide the default read/write configurations
Message sequences can vary depending on how many pads (lines) are
required to address the chip (mode & dummy), how many data pads (lines)
are required to write out to the chip which will determine speed
amongst other things which are detailed by the SFDP specification. We
are able to use multiple configurations for each chip, but they need
to me matched to a device's capabilities. These configurations are
listed in preference order - most preferred first.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
249516c9c3 mtd: st_spi_fsm: Update the flash Volatile Configuration Register
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for updating a chip's VCR.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
0de08e43cd mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing mode
Most Serial Flash chips support 24bit addressing as a default but more
recent incarnations can support 32bit. Based on information provided
though platform specific data and capabilities we can determine whether
or not our current chip can. This patch provides a means to setup the
FSM message sequence to put the chip into 32bit mode.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:18 -07:00
Lee Jones
0ea7d70693 mtd: st_spi_fsm: Add a check to if the chip can handle an SoC reset
Based on information we can obtain though platform specific data and/or
chip capabilities we are able to determine whether or not we can handle
a SoC reset or not. To find out why this is important please read the
comment provided in the patch.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:17 -07:00
Lee Jones
88cccb8911 mtd: st_spi_fsm: Prepare read/write sequences according to configuration
Firstly we search for our preference read/write configuration based on a
given chip's capabilities. Then we actually set up the message sequence
accordingly.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:17 -07:00
Lee Jones
6bd2960080 mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing mode
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for setting 32bit addressing
mode on the Flash chip.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:17 -07:00
Lee Jones
fa5ba3af20 mtd: st_spi_fsm: Provide the erase one sector sequence
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for erasing a single sector.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:17 -07:00
Lee Jones
a63984c18a mtd: st_spi_fsm: Fetch boot-device from mode pins
It's important for us to determine which device was used to boot from in
order to make some correct decisions surrounding Power Management. On
each of the platforms which support the FSM this is communicated via
a set of mode pins held in the system configuration area. This patch
determine the boot device and stores the result.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:17 -07:00
Lee Jones
97ccf2d253 mtd: st_spi_fsm: Prepare the read/write FSM message sequence(s)
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare read/write FSM message sequence(s) based on chip capability
and configuration.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:16 -07:00
Lee Jones
3b5d198193 mtd: st_spi_fsm: Use device size to determine address width
Take some known parameters, namely size and number of sectors and use
them to determine weather a device can support 32bit addressing or not.
If it can, set the associated flash capability flag for latter use.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:16 -07:00
Lee Jones
089812740d mtd: st_spi_fsm: Search for preferred FSM message sequence configurations
Here we provide a means to traverse though all supplied FSM message
sequence configurations and pick one based on our chip's capabilities.
The first one we match will be the preferred one, as they are
presented in order of preference.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:16 -07:00
Lee Jones
24fec651d1 mtd: st_spi_fsm: Dynamically setup flash device based on JEDEC ID
Using previously added infrastructure we can now extract a device's JEDEC
ID, compare it to a list of known and supported devices and make assumptions
based on known characteristics of a given chip.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:15 -07:00
Lee Jones
11d7f82663 mtd: st_spi_fsm: Provide device look-up table
Supply a lookup table of all the devices we intend to support. This table
is used to store device information such as; a human readable device name,
their JEDEC ID (plus the extended version), sector size and amount, a bit
store of a device's capabilities, its maximum running frequency and
possible use of a per-device configuration call-back.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:15 -07:00
Lee Jones
5549fbd514 mtd: devices: Provide header for shared OPCODEs and SFDP commands
JEDEC have helped to standardise a great deal of the commands which
can be issued to a Serial Flash devices. Many of the Serial Flash
Discoverable Parameters (SFDP) commands are generic across devices.
This patch provides a shared point where these commands can be
defined.

Suggested-by: Mark Brown <broonie@kernel.org>
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:15 -07:00
Lee Jones
1bd512b562 mtd: st_spi_fsm: Add support for JEDEC ID extraction
Once we start supporting devices it will be handy go detect them
dynamically. This will be done using the chip's unique JEDEC ID. This
patch allows us to extract a device's JEDEC ID using the a predefined
FSM register write sequence.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:15 -07:00
Lee Jones
030e82dc63 mtd: st_spi_fsm: Supply a method to read from the FSM's FIFO
When invoked the driver will attempt to read any available data from
the FSM's data register. Any data collected from this FIFO would have
originated from the flash chip.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:14 -07:00
Lee Jones
3c8b85b340 mtd: st_spi_fsm: Supply framework for device requests
The FSM hardware works by setting a predetermined sequence of register
writes. Rather than open coding them inside each functional block we're
going to define them in a series of formatted 'sequence structures'.
This patch provides the framework which shall be used for every action.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:14 -07:00
Lee Jones
86f309fd8f mtd: st_spi_fsm: Initialise and configure the FSM for normal working conditions
This patch uses default values to initialise a connected flash chip. This
includes; a device soft reset, setting of a safe working frequency, a
switch into Fast Sequencing Mode, configuring of timing data and a purge
of the FIFO.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:14 -07:00
Lee Jones
bc09fb5756 mtd: st_spi_fsm: Supply all register address and bit logic defines
Here we provide the FSM's register addresses, register bit names/offsets
and some commands which will prove useful as we start bulk the FMS's
driver out with functionality.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:14 -07:00
Lee Jones
d90db4a074 mtd: st_spi_fsm: Allocate resources and register with MTD framework
This is a new driver. It's used to communicate with a special type of
optimised Serial Flash Controller called the FSM. The FSM uses a subset
of the SPI protocol to communicate with supported NOR-Flash devices.

Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 04:17:14 -07:00
Pekon Gupta
c7b05e9701 mtd: nand: omap: remove is_elm_present flag
'is_elm_present' flag is not used anywhere. This check is implicitely
taken care while selecting appropriate ecc-scheme via DT or board-file.

Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:55:28 -07:00
Pekon Gupta
16e69322c5 mtd: nand: omap: ecc.hwctl: clean omap_enable_hwecc_bch for redundant ECC configs
This patch
 - refactors GPMC configurations based on ecc-scheme
 - removed dependency on is_elm_present() flag, which is implicitely
   taken care by selecting appropriate ecc-scheme

Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:55:28 -07:00
Pekon Gupta
c5957a3201 mtd: nand: omap: ecc.hwctl: refactor omap_enable_hwecc_bch for ECC related GPMC configs
Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if
code is refactored based on ecc-scheme.

Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:55:27 -07:00
Pekon Gupta
7c977c3eb2 mtd: nand: omap: ecc.hwctl: rename omap3_enable_hwecc_bch to omap_enable_hwecc_bch
This patch
 - renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep
   nomenclature independent of any device family.
 - using '__maybe_unused' instead of `ifdef based conditional compilation
   to suppress warning for un-used functions

Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:55:27 -07:00
Pekon Gupta
7bcd1dca1d mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch8 in omap_calculate_ecc_bch
merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+---------------------+-------------------------------------------------------+
|ecc-scheme           | nand_chip->calculate() after this patch               |
+---------------------+-------------------------------------------------------+
|HAM1_ECC             | omap_calculate_ecc()                                  |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch()                              |
|BCH4_HW              | omap_calculate_ecc_bch()                              |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()|
|BCH8_HW              | omap_calculate_ecc_bch()                              |
+---------------------+-------------------------------------------------------+

Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:30:27 -07:00
Pekon Gupta
2c9f2365d1 mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in omap_calculate_ecc_bch
merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH4_CODE_HW and
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes

+---------------------+-------------------------------------------------------+
|ecc-scheme           | nand_chip->calculate() after this patch               |
+---------------------+-------------------------------------------------------+
|HAM1_ECC             | omap_calculate_ecc()                                  |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()|
|BCH4_HW              | omap_calculate_ecc_bch()                              |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8()                            |
|BCH8_HW              | omap_calculate_ecc_bch()                              |
+---------------------+-------------------------------------------------------+

Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:30:27 -07:00
Pekon Gupta
f5dc06fb71 mtd: nand: omap: ecc.calculate: refactor omap_calculate_ecc_bch for BCHx_HW ecc-scheme
OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms.
+------+------------------------------------+---------------+---------------+
| Algo | ECC scheme                         |ECC calculation|Error detection|
+------+------------------------------------+---------------+---------------+
|      |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW  |H/W (GPMC)     |S/W            |
| BCH4 |OMAP_ECC_BCH4_CODE_HW               |H/W (GPMC)     |H/W (ELM)      |
+------+------------------------------------+---------------+---------------+
|      |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW  |H/W (GPMC)     |S/W            |
| BCH8 |OMAP_ECC_BCH8_CODE_HW               |H/W (GPMC)     |H/W (ELM)      |
+------+------------------------------------+---------------+---------------+

This patch refactors omap_calculate_ecc_bch() so that
 - separate out ecc-scheme specific code so that common-code can be reused
   between different implementations of same ECC algorithm.
 - new ecc-schemes can be added with ease in future.

Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:30:27 -07:00
Pekon Gupta
a4c7ca004d mtd: nand: omap: ecc.calculate: rename omap3_calculate_ecc_bch to omap_calculate_ecc_bch
rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to
keep nomenclature independent of any device family.

Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20 02:30:26 -07:00