Commit Graph

1115 Commits

Author SHA1 Message Date
Bjorn Helgaas
66aa51ce8b Merge branch 'pci/host-faraday' into next
* pci/host-faraday:
  PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver
  PCI: Add DT bindings for Faraday Technology PCI Host Bridge
2017-04-28 10:32:44 -05:00
Lorenzo Pieralisi
bc636ee945 PCI: versatile: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh@kernel.org>
2017-04-24 13:53:18 -05:00
Lorenzo Pieralisi
3e02dc439b PCI: tegra: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use correct memory mapping attributes to map config space
regions to enforce configuration space non-posted writes behaviour.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
2017-04-24 13:53:17 -05:00
Lorenzo Pieralisi
26b758f775 PCI: xgene: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tanmay Inamdar <tinamdar@apm.com>
2017-04-24 13:53:16 -05:00
Lorenzo Pieralisi
868564da65 PCI: iproc-platform: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
2017-04-24 13:53:16 -05:00
Lorenzo Pieralisi
995b76e48f PCI: rockchip: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wenrui Li <wenrui.li@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-24 13:53:15 -05:00
Lorenzo Pieralisi
cd00f084ed PCI: xilinx-nwl: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2017-04-24 13:53:15 -05:00
Lorenzo Pieralisi
eb21f9e820 PCI: xilinx: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2017-04-24 13:53:14 -05:00
Brian Norris
b0308c5419 PCI: rockchip: Modularize
Now that we've exported pci_remap_iospace() and added proper remove()
support, there's no reason this can't be a loadable module.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-21 11:01:46 -05:00
Brian Norris
073d3dbe9a PCI: rockchip: Add remove() support
Currently, if we try to unbind the platform device, the remove will
succeed, but the removal won't undo most of the registration, leaving
partially-configured PCI devices in the system.

This allows, for example, a simple 'lspci' to crash the system, as it will
try to touch the freed (via devm_*) driver structures, e.g., on RK3399:

  # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind
  # lspci

So let's implement device remove().

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-21 10:54:35 -05:00
Elena Reshetova
24196f0c7d PCI: hv: Convert hv_pci_dev.refs from atomic_t to refcount_t
refcount_t type and corresponding API should be used instead of atomic_t
when the variable is used as a reference counter.  This allows to avoid
accidental refcounter overflows that might lead to use-after-free
situations.

Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
Signed-off-by: Hans Liljestrand <ishkamiel@gmail.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: David Windsor <dwindsor@gmail.com>
Reviewed-by: Stephen Hemminger <sthemmin@microsoft.com>
2017-04-18 09:02:48 -05:00
Shawn Lin
64d6ea602c PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port
All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.

Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: jeffy.chen <jeffy.chen@rock-chips.com>
2017-04-11 16:27:02 -05:00
K. Y. Srinivasan
59c58ceeea PCI: hv: Allocate interrupt descriptors with GFP_ATOMIC
The memory allocation here needs to be non-blocking.  Fix the issue.

Signed-off-by: K. Y. Srinivasan <kys@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Long Li <longli@microsoft.com>
Cc: <stable@vger.kernel.org>
2017-04-04 14:00:01 -05:00
K. Y. Srinivasan
433fcf6b7b PCI: hv: Specify CPU_AFFINITY_ALL for MSI affinity when >= 32 CPUs
When we have 32 or more CPUs in the affinity mask, we should use a special
constant to specify that to the host. Fix this issue.

Signed-off-by: K. Y. Srinivasan <kys@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Long Li <longli@microsoft.com>
Cc: <stable@vger.kernel.org>
2017-04-04 13:58:20 -05:00
Shawn Lin
55021718b9 PCI: rockchip: Advertise 128-byte Read Completion Boundary support
Rockchip Root Ports support either 64 or 128 byte Read Completion Boundary
(RCB).  Set the RCB bit in the Link Control register to indicate this.

A 128 byte RCB significantly improves performance of NVMe with libaio.

[bhelgaas: changelog]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
2017-04-03 16:04:48 -05:00
Tomasz Nowicki
feb199ebef PCI: thunder-pem: Fix legacy firmware PEM-specific resources
SZ_16M PEM resource size includes PEM-specific register and its children
resources. Reservation of the whole SZ_16M range leads to child device
driver failure when pcieport driver is requesting resources:

  pcieport 0004:1f:00.0: can't enable device: BAR 0 [mem 0x87e0c0f00000-0x87e0c0ffffff 64bit] not claimed

So we cannot reserve full 16M here and instead we want to reserve
PEM-specific register only which is SZ_64K.

At the end increase PEM resource to SZ_16M since this is what
thunder_pem_init() call expects for proper initialization.

Fixes: 9abb27c759 ("PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller")
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.10+
2017-04-03 15:10:21 -05:00
Russell King
b8e82c1bdd PCI: mvebu: Avoid changing the SCC bit in the Link Status register
It seems on later Armada 38x, the slot clock configuration bit is not
read-only, but can be written.  This means that our RW1C protection ends up
clearing this bit when the link control register is written.

Adjust the mask so that we only avoid writing '1' bits to the RW1C bits of
this register (bits 15 and 14 of the link status) rather than masking out
all the status register bits.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-25 12:19:10 -05:00
Linus Walleij
d3c68e0a7e PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver
Add a host bridge driver for the Faraday Technology FPPCI100 host bridge,
used for Cortina Systems Gemini SoC (SL3516) PCI Host Bridge.

This code is inspired by the out-of-tree OpenWRT patch and then extensively
rewritten for device tree and using the modern helpers to cut down and
modernize the code to all new PCI frameworks.  A driver exists in U-Boot as
well.

Tested on the ITian Square One SQ201 NAS with the following result in the
boot log (trimmed to relevant parts):

  OF: PCI: host bridge /soc/pci@50000000 ranges:
  OF: PCI:    IO 0x50000000..0x500fffff -> 0x00000000
  OF: PCI:   MEM 0x58000000..0x5fffffff -> 0x58000000
  ftpci100 50000000.pci: PCI host bridge to bus 0000:00
  pci_bus 0000:00: root bus resource [bus 00-ff]
  pci_bus 0000:00: root bus resource [io  0x0000-0xfffff]
  pci_bus 0000:00: root bus resource [mem 0x58000000-0x5fffffff]
  ftpci100 50000000.pci:
    DMA MEM1 BASE: 0x0000000000000000 -> 0x0000000007ffffff config 00070000
  ftpci100 50000000.pci:
    DMA MEM2 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
  ftpci100 50000000.pci:
    DMA MEM3 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
  PCI: bus0: Fast back to back transfers disabled
  pci 0000:00:00.0: of_irq_parse_pci() failed with rc=-22
  pci 0000:00:0c.0: BAR 0: assigned [mem 0x58000000-0x58007fff]
  pci 0000:00:09.2: BAR 0: assigned [mem 0x58008000-0x580080ff]
  pci 0000:00:09.0: BAR 4: assigned [io  0x1000-0x101f]
  pci 0000:00:09.1: BAR 4: assigned [io  0x1020-0x103f]
  pci 0000:00:09.0: enabling device (0140 -> 0141)
  pci 0000:00:09.0: HCRESET not completed yet!
  pci 0000:00:09.1: enabling device (0140 -> 0141)
  pci 0000:00:09.1: HCRESET not completed yet!
  pci 0000:00:09.2: enabling device (0140 -> 0142)
  rt61pci 0000:00:0c.0: enabling device (0140 -> 0142)
  ieee80211 phy0: rt2x00_set_chip: Info - Chipset detected -
     rt: 2561, rf: 0003, rev: 000c
  ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
  ehci-pci: EHCI PCI platform driver
  ehci-pci 0000:00:09.2: EHCI Host Controller
  ehci-pci 0000:00:09.2: new USB bus registered, assigned bus number 1
  ehci-pci 0000:00:09.2: irq 125, io mem 0x58008000
  ehci-pci 0000:00:09.2: USB 2.0 started, EHCI 1.00
  hub 1-0:1.0: USB hub found
  hub 1-0:1.0: 4 ports detected
  uhci_hcd: USB Universal Host Controller Interface driver
  uhci_hcd 0000:00:09.0: UHCI Host Controller
  uhci_hcd 0000:00:09.0: new USB bus registered, assigned bus number 2
  uhci_hcd 0000:00:09.0: HCRESET not completed yet!
  uhci_hcd 0000:00:09.0: irq 123, io base 0x00001000
  hub 2-0:1.0: USB hub found
  hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
  uhci_hcd 0000:00:09.1: UHCI Host Controller
  uhci_hcd 0000:00:09.1: new USB bus registered, assigned bus number 3
  uhci_hcd 0000:00:09.1: HCRESET not completed yet!
  uhci_hcd 0000:00:09.1: irq 124, io base 0x00001020
  hub 3-0:1.0: USB hub found
  hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
  scsi 0:0:0:0: Direct-Access     USB      Flash Disk       1.00 PQ: 0 ANSI: 2
  sd 0:0:0:0: [sda] 7900336 512-byte logical blocks: (4.04 GB/3.77 GiB)
  sd 0:0:0:0: [sda] Write Protect is off
  sd 0:0:0:0: [sda] No Caching mode page found
  sd 0:0:0:0: [sda] Assuming drive cache: write through
   sda: sda1 sda2 sda3
  sd 0:0:0:0: [sda] Attached SCSI removable disk
  ieee80211 phy0: rt2x00lib_request_firmware: Info -
     Loading firmware file 'rt2561s.bin'
  ieee80211 phy0: rt2x00lib_request_firmware: Info -
     Firmware detected - version: 0.8
  IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready

  $ lspci
  00:00.0 Class 0600: 159b:4321
  00:09.2 Class 0c03: 1106:3104
  00:09.0 Class 0c03: 1106:3038
  00:09.1 Class 0c03: 1106:3038
  00:0c.0 Class 0280: 1814:0301

  $ cat /proc/interrupts
	     CPU0
  123:          0       PCI   0 Edge      uhci_hcd:usb2
  124:          0       PCI   1 Edge      uhci_hcd:usb3
  125:        159       PCI   2 Edge      ehci_hcd:usb1
  126:       1082       PCI   3 Edge      rt61pci

  $ cat /proc/iomem
  50000000-500000ff : /soc/pci@50000000
  58000000-5fffffff : Gemini PCI MEM
    58000000-58007fff : 0000:00:0c.0
      58000000-58007fff : 0000:00:0c.0
    58008000-580080ff : 0000:00:09.2
      58008000-580080ff : ehci_hcd

The EHCI USB hub works fine; I can mount and manage files and the IRQs just
keep ticking up.  I can issue iwlist wlan0 scanning and see all the WLANs
here.  I don't have wpa_supplicant so have not tried connecting to them.

[bhelgaas: fold in %pap change from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Janos Laube <janos.dev@gmail.com>
CC: Paulius Zaleckas <paulius.zaleckas@gmail.com>
CC: Hans Ulli Kroll <ulli.kroll@googlemail.com>
CC: Florian Fainelli <f.fainelli@gmail.com>
CC: Feng-Hsin Chiang <john453@faraday-tech.com>
CC: Greentime Hu <green.hu@gmail.com>
2017-03-24 10:31:17 -05:00
Long Li
414428c5da PCI: hv: Lock PCI bus on device eject
A PCI_EJECT message can arrive at the same time we are calling
pci_scan_child_bus() in the workqueue for the previous PCI_BUS_RELATIONS
message or in create_root_hv_pci_bus().  In this case we could potentially
modify the bus from multiple places.

Properly lock the bus access.

Thanks Dexuan Cui <decui@microsoft.com> for pointing out the race condition
in create_root_hv_pci_bus().

Reported-by: Xiaofeng Wang <xiaofwan@redhat.com>
Signed-off-by: Long Li <longli@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-03-24 09:54:56 -05:00
Long Li
d3a78d8bf7 PCI: hv: Properly handle PCI bus remove
hv_pci_devices_present() is called in hv_pci_remove() when we remove a PCI
device from the host, e.g., by disabling SR-IOV on a device.  In
hv_pci_remove(), the bus is already removed before the call, so we don't
need to rescan the bus in the workqueue scheduled from
hv_pci_devices_present().

By introducing bus state hv_pcibus_removed, we can avoid this situation.

Reported-by: Xiaofeng Wang <xiaofwan@redhat.com>
Signed-off-by: Long Li <longli@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-03-24 09:50:25 -05:00
Brian Norris
deb518f6ae PCI: rockchip: Make 'return 0' more obvious in probe()
There's no way to get here with 'err != 0'.  Just return 0 to be more
obvious and prevent future changes from accidentally erroring out here
without going through the right error paths.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-23 17:24:34 -05:00
Bjorn Helgaas
73edd2b180 PCI: rockchip: Unindent rockchip_pcie_set_power_limit()
If regulator_get_current_limit() returns 0 or error, return early so the
body of the function doesn't have to be indented as the body of an "if"
statement.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-23 17:21:26 -05:00
Tomasz Nowicki
9abb27c759 PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller
During early days of PCI quirks support, ThunderX firmware did not provide
PNP0c02 node with PCI configuration space and PEM-specific register ranges.
This means that for legacy FW we are not reserving these resources and
cannot gather PEM-specific resources for further PEM initialization.

To support already deployed legacy FW, calculate PEM-specific ranges and
provide resources reservation as fallback scenario into PEM driver when we
could not gather PEM reg base from ACPI tables.

Tested-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@caviumnetworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robert Richter <rrichter@cavium.com>
CC: stable@vger.kernel.org	# v4.10+
2017-03-23 17:11:26 -05:00
Tomasz Nowicki
81caa91b72 PCI: thunder-pem: Use Cavium assigned hardware ID for ThunderX host controller
"CAV" is the only PNP/ACPI hardware ID vendor prefix assigned to Cavium so
fix this as it should be from day one.

Fixes: 44f22bd91e ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
Tested-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robert Richter <rrichter@cavium.com>
CC: stable@vger.kernel.org	# v4.10+
2017-03-23 17:10:10 -05:00
Brian Norris
5fcaa0051d PCI: rockchip: Handle regulator_get_current_limit() failure correctly
regulator_get_current_limit() can return negative error codes.  We saved
the return value in an unsigned "curr", and a subsequent check interpreted
a negative error code as a positive (invalid) current limit.

Save the return code as a signed value, which avoids messages like this,
seen on Samsung Chromebook Plus:

  rockchip-pcie f8000000.pcie: invalid power supply

[bhelgaas: changelog]
Fixes: 4816c4c7b8 ("PCI: rockchip: Provide captured slot power limit and scale")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-23 17:09:12 -05:00
Jon Mason
e584b06c47 PCI: iproc: Add PCI_DOMAIN dependency to PCI Kconfig
2+ PCI devices fail to be discovered due to each bus having the same PCI
domain.  This is because the domain defined in the device tree file is not
being added due to PCI_DOMAIN not being enabled.  So, every PCI bus has a
domain of zero.  When PCI_DOMAIN is selected by the Kconfig, it picks up
the domain defined in the device tree file and everything works as
expected.

Since both PCIE_IPROC_PLATFORM and PCIE_IPROC_BCMA need PCI_DOMAIN, move
it to PCIE_IPROC so it will be automatically selected for both.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-16 15:15:09 -05:00
Thomas Petazzoni
393bf9b38a PCI: mvebu: Remove useless MSI enabling code
Since commit fcc392d501 ("irqchip/armada-370-xp: Use the generic MSI
infrastructure"), the irqchip driver used on Armada 370, XP, 375, 38x, 39x
for the MPIC interrupt controller has been converted to use the generic MSI
infrastructure.

Since this commit, it is no longer registering an msi_controller structure
with the of_pci_msi_chip_add() function. Therefore, having the PCI driver
used on the same platform calling of_pci_find_msi_chip_by_node() is pretty
useless.

The MSI resolution is now done in the generic interrupt resolution code,
since the MSI controller is an irq domain attached to the interrupt
controller node, which is pointed to by the msi-parent DT property in the
PCIe controller node.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-14 15:09:32 -05:00
Thomas Petazzoni
f21a8b1b68 PCI: aardvark: Move to MSI handling using generic MSI support
The MSI support introduced with the initial Aardvark driver was based
on the msi_controller structure and the of_pci_msi_chip_add() /
of_pci_find_msi_chip_by_node() API, which are being deprecated in
favor of the generic MSI support.

Update the Aardvark driver to use the generic MSI support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-14 15:06:33 -05:00
Bjorn Helgaas
6e347b5e05 PCI: iproc: Save host bridge window resource in struct iproc_pcie
The host bridge memory window resource is inserted into the iomem_resource
tree and cannot be deallocated until the host bridge itself is removed.

Previously, the window was on the stack, which meant the iomem_resource
entry pointed into the stack and was corrupted as soon as the probe
function returned, which caused memory corruption and errors like this:

  pcie_iproc_bcma bcma0:8: resource collision: [mem 0x40000000-0x47ffffff] conflicts with PCIe MEM space [mem 0x40000000-0x47ffffff]

Move the memory window resource from the stack into struct iproc_pcie so
its lifetime matches that of the host bridge.

Fixes: c3245a5664 ("PCI: iproc: Request host bridge window resources")
Reported-and-tested-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.8+
2017-03-09 11:27:07 -06:00
Linus Torvalds
e27fd02d92 pci-v4.11-fixes-1
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Merge tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

 - fix NULL pointer dereferences in many DesignWare-based drivers due to
   refactoring error

 - fix Altera config write breakage due to my refactoring error

* tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: altera: Fix TLP_CFG_DW0 for TLP write
  PCI: dwc: Fix crashes seen due to missing assignments
2017-03-03 16:44:21 -08:00
Ley Foon Tan
2a7275a3d8 PCI: altera: Fix TLP_CFG_DW0 for TLP write
eb5767122f ("PCI: altera: Simplify TLB_CFG_DW0 usage") used
TLP_FMTTYPE_CFGRD* (instead of TLP_FMTTYPE_CFGWR*) for TLP writes, which
causes writing to configuration space to fail.  Fix it by using correct
FMTTYPE for write operation.

Fixes: eb5767122f ("PCI: altera: Simplify TLB_CFG_DW0 usage")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.9+
2017-02-28 15:06:29 -06:00
Linus Torvalds
ac1820fb28 This is a tree wide change and has been kept separate for that reason.
Bart Van Assche noted that the ib DMA mapping code was significantly
 similar enough to the core DMA mapping code that with a few changes
 it was possible to remove the IB DMA mapping code entirely and
 switch the RDMA stack to use the core DMA mapping code.  This resulted
 in a nice set of cleanups, but touched the entire tree.  This branch
 will be submitted separately to Linus at the end of the merge window
 as per normal practice for tree wide changes like this.
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Merge tag 'for-next-dma_ops' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma

Pull rdma DMA mapping updates from Doug Ledford:
 "Drop IB DMA mapping code and use core DMA code instead.

  Bart Van Assche noted that the ib DMA mapping code was significantly
  similar enough to the core DMA mapping code that with a few changes it
  was possible to remove the IB DMA mapping code entirely and switch the
  RDMA stack to use the core DMA mapping code.

  This resulted in a nice set of cleanups, but touched the entire tree
  and has been kept separate for that reason."

* tag 'for-next-dma_ops' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (37 commits)
  IB/rxe, IB/rdmavt: Use dma_virt_ops instead of duplicating it
  IB/core: Remove ib_device.dma_device
  nvme-rdma: Switch from dma_device to dev.parent
  RDS: net: Switch from dma_device to dev.parent
  IB/srpt: Modify a debug statement
  IB/srp: Switch from dma_device to dev.parent
  IB/iser: Switch from dma_device to dev.parent
  IB/IPoIB: Switch from dma_device to dev.parent
  IB/rxe: Switch from dma_device to dev.parent
  IB/vmw_pvrdma: Switch from dma_device to dev.parent
  IB/usnic: Switch from dma_device to dev.parent
  IB/qib: Switch from dma_device to dev.parent
  IB/qedr: Switch from dma_device to dev.parent
  IB/ocrdma: Switch from dma_device to dev.parent
  IB/nes: Remove a superfluous assignment statement
  IB/mthca: Switch from dma_device to dev.parent
  IB/mlx5: Switch from dma_device to dev.parent
  IB/mlx4: Switch from dma_device to dev.parent
  IB/i40iw: Remove a superfluous assignment statement
  IB/hns: Switch from dma_device to dev.parent
  ...
2017-02-25 13:45:43 -08:00
Linus Torvalds
60e8d3e116 pci-v4.11-changes
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Merge tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:

 - add ASPM L1 substate support

 - enable PCIe Extended Tags when supported

 - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx

 - increase VPD access timeout

 - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432

 - use new pci_irq_alloc_vectors() in more drivers

 - fix MSI affinity memory leak

 - remove unused MSI interfaces and update documentation

 - remove unused AER .link_reset() callback

 - avoid pci_lock / p->pi_lock deadlock seen with perf

 - serialize sysfs enable/disable num_vfs operations

 - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and
   refactor so we can support both hosts and endpoints

 - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers

 - add Rockchip system power management support

 - add Thunder-X cn81xx and cn83xx support

 - add Exynos 5440 PCIe PHY support

* tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits)
  PCI: dwc: Remove dependency of designware on CONFIG_PCI
  PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host
  PCI: dwc: Split pcie-designware.c into host and core files
  PCI: dwc: designware: Fix style errors in pcie-designware.c
  PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()
  PCI: dwc: all: Split struct pcie_port into host-only and core structures
  PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()
  PCI: dwc: all: Rename cfg_read/cfg_write to read/write
  PCI: dwc: all: Use platform_set_drvdata() to save private data
  PCI: dwc: designware: Move register defines to designware header file
  PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code
  PCI: dra7xx: Group PHY API invocations
  PCI: dra7xx: Enable MSI and legacy interrupts simultaneously
  PCI: dra7xx: Add support to force RC to work in GEN1 mode
  PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional()
  PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory
  PCI: exynos: Support the PHY generic framework
  Documentation: binding: Modify the exynos5440 PCIe binding
  phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
  Documentation: samsung-phy: Add exynos-pcie-phy binding
  ...
2017-02-23 11:53:22 -08:00
Bjorn Helgaas
9e38637a08 Merge branch 'pci/host-xilinx' into next
* pci/host-xilinx:
  PCI: xilinx-nwl: Remove mask for messages not supported by AXI
  PCI: xilinx: Configure PCIe MPS settings
2017-02-21 15:16:12 -06:00
Bjorn Helgaas
9d534265bd Merge branch 'pci/host-xgene' into next
* pci/host-xgene:
  PCI: xgene: Configure PCIe MPS settings
  PCI: xgene: Fix double free on init error
2017-02-21 15:16:08 -06:00
Bjorn Helgaas
f08bf55e69 Merge branch 'pci/host-versatile' into next
* pci/host-versatile:
  PCI: versatile: Configure PCIe MPS settings
2017-02-21 15:15:54 -06:00
Bjorn Helgaas
b98a7f7509 Merge branch 'pci/host-thunder' into next
* pci/host-thunder:
  PCI: thunder-pem: Add support for cn81xx and cn83xx SoCs
2017-02-21 15:15:49 -06:00
Bjorn Helgaas
bcea623c65 Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip:
  PCI: rockchip: Set vendor ID from local core config space
  PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource list
  PCI: rockchip: Mark PM functions as __maybe_unused
  PCI: rockchip: Use readl_poll_timeout() instead of open-coding it
  PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"
  PCI: rockchip: Add system PM support
2017-02-21 15:15:44 -06:00
Bjorn Helgaas
56195e9d1d Merge branch 'pci/host-rcar' into next
* pci/host-rcar:
  PCI: rcar: Use of_device_get_match_data() to simplify probe
  PCI: rcar: Add compatible string for r8a7796
  PCI: rcar: Return -ENODEV from host bridge probe when no card present
2017-02-21 15:15:39 -06:00
Bjorn Helgaas
dda718926c Merge branch 'pci/host-mvebu' into next
* pci/host-mvebu:
  PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms
  PCI: mvebu: Handle changes to the bridge windows while enabled
2017-02-21 15:15:34 -06:00
Bjorn Helgaas
68094b4b8d Merge branch 'pci/host-iproc' into next
* pci/host-iproc:
  PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS
  PCI: iproc: Configure PCIe MPS settings
  PCI: iproc: Use of_device_get_match_data() to simplify probe
2017-02-21 15:15:05 -06:00
Bjorn Helgaas
5dcda98a3b Merge branch 'pci/host-hv' into next
* pci/host-hv:
  PCI: hv: Use device serial number as PCI domain
  PCI: hv: Fix wslot_to_devfn() to fix warnings on device removal
2017-02-21 15:14:31 -06:00
Bjorn Helgaas
d952097158 Merge branch 'pci/host-hisi' into next
* pci/host-hisi:
  PCI: generic: Call pci_fixup_irqs() only on ARM
  PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports
  PCI: hisi: Rename config space accessors to remove "acpi"
  PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers
  PCI: hisi: Use of_device_get_match_data() to simplify probe

Conflicts:
	drivers/pci/dwc/pcie-hisi.c
2017-02-21 15:14:18 -06:00
Bjorn Helgaas
1a55761392 Merge branch 'pci/host-altera' into next
* pci/host-altera:
  PCI: altera: Extract TLP completion status correctly
2017-02-21 15:12:18 -06:00
Kishon Vijay Abraham I
950bf6388b PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory
Group all the PCI drivers that use DesignWare core in dwc directory.
dwc IP is capable of operating in both host mode and device mode and
keeping it inside the *host* directory is misleading.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Minghuan Lian <minghuan.Lian@freescale.com>
Cc: Mingkai Hu <mingkai.hu@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-02-21 14:59:53 -06:00
Yadi Hu
8ca6e0a75a PCI: altera: Extract TLP completion status correctly
Previously we extracted 'Completion Status' from b14:12, but it is actually
b15:13.  Extract it from the correct bits.

Signed-off-by: Hu Yadi<yadi.hu@windriver.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-02-17 14:20:26 -06:00
Shawn Lin
5800790a92 PCI: rockchip: Set vendor ID from local core config space
The TRM says the vendor ID in the RC's configure space can be rewritten
and the value must be the same as the value read from the local core
configure space.  But we misread that and didn't notice it before.  Actually
we should only able to rewrite it from the local core configure space.

Fix that issue to make lspci show the correct IP vendor infomation.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-17 14:13:05 -06:00
Haiyang Zhang
4a9b0933bd PCI: hv: Use device serial number as PCI domain
Use the device serial number as the PCI domain.  The serial numbers start
with 1 and are unique within a VM.  So names, such as VF NIC names, that
include domain number as part of the name, can be shorter than that based
on part of bus UUID previously.  The new names will also stay same for VMs
created with copied VHD and same number of devices.

Signed-off-by: Haiyang Zhang <haiyangz@microsoft.com>
Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
2017-02-17 13:53:29 -06:00
Shawn Lin
f1d722b607 PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource list
rockchip_pcie_probe() calls of_pci_get_host_bridge_resources() to parse
resources from DT and build a resource list.  The caller is responsible for
disposing of the resource list.  This is normally done by
pci_release_host_bridge_dev() when the host bridge is removed.

If the host bridge probe fails, dispose of the resource list in the probe
error path.

[bhelgaas: changelog]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-10 15:42:01 -06:00
Dexuan Cui
60e2e2fbaf PCI: hv: Fix wslot_to_devfn() to fix warnings on device removal
The devfn of 00:02.0 is 0x10.  devfn_to_wslot(0x10) == 0x2, and
wslot_to_devfn(0x2) should be 0x10, while it's 0x2 in the current code.

Due to this, hv_eject_device_work() -> pci_get_domain_bus_and_slot()
returns NULL and pci_stop_and_remove_bus_device() is not called.

Later when the real device driver's .remove() is invoked by
hv_pci_remove() -> pci_stop_root_bus(), some warnings can be noticed
because the VM has lost the access to the underlying device at that
time.

Signed-off-by: Jake Oshins <jakeo@microsoft.com>
Signed-off-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Haiyang Zhang <haiyangz@microsoft.com>
CC: stable@vger.kernel.org
CC: K. Y. Srinivasan <kys@microsoft.com>
CC: Stephen Hemminger <sthemmin@microsoft.com>
2017-02-10 15:18:46 -06:00
Bharat Kumar Gogada
26b54be568 PCI: xilinx-nwl: Remove mask for messages not supported by AXI
Remove support for vendor-defined messages which are not supported by AXI.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-10 14:22:17 -06:00
Bjorn Helgaas
7da7a1a66e PCI: xgene: Configure PCIe MPS settings
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy.

Based-on-patch-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-10 11:36:14 -06:00
Dongdong Liu
3fb5561879 PCI: generic: Call pci_fixup_irqs() only on ARM
pci_fixup_irqs() is problematic because:

  - it's called when we enumerate a host bridge, so we don't fixup IRQs for
    hot-added PCI devices, and

  - it fixes up IRQs for all PCI devices in the system, so if we call it
    multiple times, e.g., if we have several host controllers, we may
    reallocate an IRQ for a device after a driver has already claimed it.

We plan to replace pci_fixup_irqs() soon, but we still need it on ARM
because we don't have any other generic method for doing this.

On ARM64, we don't need pci_fixup_irqs() because we do IRQ setup when we
bind a driver to the device (in the pci_device_probe() ->
pcibios_alloc_irq() path).

pci-host-common.c is currently only used on ARM and ARM64.  In principle,
it could be used on x86, and we wouldn't want pci_fixup_irqs() there
either, because x86 does IRQ setup in the pci_enable_device() path.

[bhelgaas: changelog, use #ifdef ARM, not #ifndef ARM64]
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2017-02-09 09:13:20 -06:00
Bjorn Helgaas
4788316f74 PCI: hisi: Rename config space accessors to remove "acpi"
There's nothing ACPI-specific about the config space accessors
hisi_pcie_acpi_rd_conf() and hisi_pcie_acpi_wr_conf(), and they're used for
both the ACPI and the DT driver model.

Rename them to hisi_pcie_rd_conf() and hisi_pcie_wr_conf().  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-09 09:13:20 -06:00
Bjorn Helgaas
70bc1b684b PCI: versatile: Configure PCIe MPS settings
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy.

Based-on-patch-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-08 15:42:26 -06:00
Bjorn Helgaas
ec6bd78a09 PCI: xilinx: Configure PCIe MPS settings
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy.

Based-on-patch-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-08 15:37:47 -06:00
Jon Mason
4d4836ab70 PCI: iproc: Configure PCIe MPS settings
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy.

[bhelgaas: changelog]
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
2017-02-08 15:20:09 -06:00
Lucas Stach
8ed81ec82a PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms
The current default of 20ms cause some devices, which are slow to
initialize, to not show up during the bus scanning.  Change this to the
PCIe spec mandated 100ms and document this in the DT binding.

From PCIe base spec rev 3.0, chapter "6.6.1. Conventional Reset":

  To allow components to perform internal initialization, system software
  must wait a specified minimum period following the end of a Conventional
  Reset of one or more devices before it is permitted to issue
  Configuration Requests to those devices.

  With a Downstream Port that does not support Link speeds greater than 5.0
  GT/s, software must wait a minimum of 100 ms before sending a
  Configuration Request to the device immediately below that Port.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
2017-02-08 13:33:57 -06:00
Dongdong Liu
a2ec199609 PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers
The PCIe controller in HiSilicon Hip06/Hip07 SoCs is not completely
ECAM-compliant.  It is non-ECAM only for the RC bus config space; for any
other bus underneath the root bus it does support ECAM access.

Add DT support for the almost-ECAM Hip06/Hip07 controllers.

[bhelgaas: drop dev->of_node test, driver name "hisi-pcie-almost-ecam"]
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
2017-02-06 16:28:29 -06:00
Shailendra Verma
792e0a6814 PCI: hisi: Use of_device_get_match_data() to simplify probe
The only way to call hisi_pcie_probe() is to match an entry in
hisi_pcie_of_match[], so match cannot be NULL.

Use of_device_get_match_data() to retrieve the soc_ops pointer.  No
functional change intended.

[bhelgaas: use of_device_get_match_data(), changelog]
Based-on-suggestion-from: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Shailendra Verma <shailendra.v@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-03 15:01:14 -06:00
Bjorn Helgaas
e5c3b3e9f0 PCI: iproc: Use of_device_get_match_data() to simplify probe
The only way to call iproc_pcie_pltfm_probe() is to match an entry in
iproc_pcie_of_match_table[], so match cannot be NULL.

Use of_device_get_match_data() to retrieve the pcie->type.  No functional
change intended.

Based-on-suggestion-from: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-01-31 16:36:32 -06:00
Bjorn Helgaas
ff1677e231 PCI: rcar: Use of_device_get_match_data() to simplify probe
This is a DT-only driver, so the only way to call rcar_pcie_probe() is to
match an entry in rcar_pcie_of_match[], so of_id cannot be NULL.

Furthermore, of_id->data can only be NULL if an rcar_pcie_of_match[] entry
has a NULL .data member.  That's a driver defect, and we don't want to
return -EINVAL, which is easy to ignore.  We'd rather take the NULL pointer
dereference so we notice the problem and fix it.

Use of_device_get_match_data() to retrieve the hw_init_fn pointer.  No
functional change intended.

Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-31 16:35:42 -06:00
Dan Carpenter
1ded56df32 PCI: xgene: Fix double free on init error
The "port" variable was allocated with devm_kzalloc() so if we free it with
kfree() it will be freed twice.  Also I changed it to propogate the error
from devm_ioremap_resource() instead of returning -ENOMEM.

Fixes: c5d4603961 ("PCI: Add MCFG quirks for X-Gene host controller")
Also-posted-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tanmay Inamdar <tinamdar@apm.com>
2017-01-30 18:17:05 -06:00
Arnd Bergmann
0b351c986a PCI: rockchip: Mark PM functions as __maybe_unused
When CONFIG_PM_SLEEP is disabled, we get harmless build warnings:

  host/pcie-rockchip.c:1267:12: error: 'rockchip_pcie_resume_noirq' defined but not used [-Werror=unused-function]
  host/pcie-rockchip.c:1240:12: error: 'rockchip_pcie_suspend_noirq' defined but not used [-Werror=unused-function]

Marking both functions as __maybe_unused avoids the warning without the
need for #ifdef around them.

Fixes: 013dd3d5e1 ("PCI: rockchip: Add system PM support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-01-30 14:52:15 -06:00
Shawn Lin
7faebda21d PCI: rockchip: Use readl_poll_timeout() instead of open-coding it
Use readl_poll_timeout() instead of open-coding it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-01-30 14:50:37 -06:00
Jason Gunthorpe
d9bf28e265 PCI: mvebu: Handle changes to the bridge windows while enabled
The PCI core will write to the bridge window config multiple times while
they are enabled.  This can lead to mbus failures like this:

 mvebu_mbus: cannot add window '4:e8', conflicts with another window
 mvebu-pcie mbus:pex@e0000000: Could not create MBus window at [mem 0xe0000000-0xe00fffff]: -22

For me this is happening during a hotplug cycle.  The PCI core is not
changing the values, just writing them twice while active.

The patch addresses the general case of any change to an active window, but
not atomically.  The code is slightly refactored so io and mem can share
more of the window logic.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
2017-01-30 09:39:38 -06:00
Bart Van Assche
5299709d0a treewide: Constify most dma_map_ops structures
Most dma_map_ops structures are never modified. Constify these
structures such that these can be write-protected. This patch
has been generated as follows:

git grep -l 'struct dma_map_ops' |
  xargs -d\\n sed -i \
    -e 's/struct dma_map_ops/const struct dma_map_ops/g' \
    -e 's/const struct dma_map_ops {/struct dma_map_ops {/g' \
    -e 's/^const struct dma_map_ops;$/struct dma_map_ops;/' \
    -e 's/const const struct dma_map_ops /const struct dma_map_ops /g';
sed -i -e 's/const \(struct dma_map_ops intel_dma_ops\)/\1/' \
  $(git grep -l 'struct dma_map_ops intel_dma_ops');
sed -i -e 's/const \(struct dma_map_ops dma_iommu_ops\)/\1/' \
  $(git grep -l 'struct dma_map_ops' | grep ^arch/powerpc);
sed -i -e '/^struct vmd_dev {$/,/^};$/ s/const \(struct dma_map_ops[[:blank:]]dma_ops;\)/\1/' \
       -e '/^static void vmd_setup_dma_ops/,/^}$/ s/const \(struct dma_map_ops \*dest\)/\1/' \
       -e 's/const \(struct dma_map_ops \*dest = \&vmd->dma_ops\)/\1/' \
    drivers/pci/host/*.c
sed -i -e '/^void __init pci_iommu_alloc(void)$/,/^}$/ s/dma_ops->/intel_dma_ops./' arch/ia64/kernel/pci-dma.c
sed -i -e 's/static const struct dma_map_ops sn_dma_ops/static struct dma_map_ops sn_dma_ops/' arch/ia64/sn/pci/pci_dma.c
sed -i -e 's/(const struct dma_map_ops \*)//' drivers/misc/mic/bus/vop_bus.c

Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Russell King <linux@armlinux.org.uk>
Cc: x86@kernel.org
Signed-off-by: Doug Ledford <dledford@redhat.com>
2017-01-24 12:23:35 -05:00
Marc Zyngier
4d191b1b63 PCI/MSI: pci-xgene-msi: Fix CPU hotplug registration handling
The conversion to the new hotplug state machine introduced a regression
where a successful hotplug registration would be treated as an error,
effectively disabling the MSI driver forever.

Fix it by doing the proper check on the return value.

Fixes: 9c248f8896 ("PCI/xgene-msi: Convert to hotplug state machine")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: Duc Dang <dhdang@apm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: stable@vger.kernel.org
2017-01-17 08:41:51 -06:00
David Daney
c5c4d3a3f4 PCI: thunder-pem: Add support for cn81xx and cn83xx SoCs
The pci-thunder-pem driver was initially developed for cn88xx SoCs.  The
cn81xx and cn83xx members of the same family of SoCs have a slightly
different configuration of interrupt resources in the PEM hardware, which
prevents the INTA legacy interrupt source from functioning with the current
driver.

There are two fixes required:

1) Don't fixup the PME interrupt on the newer SoCs as it already has the
proper value.

2) Report MSI-X Capability Table Size of 2 for the newer SoCs, so the core
MSI-X code doesn't inadvertently clobber the INTA machinery that happens to
reside immediately following the table.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-01-12 16:01:21 -06:00
Shawn Lin
afc9595ea4 PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"
Rockchip's RC produces a 100MHz reference clock but there are two methods
for the PHY to generate it:

  (1) Use the system PLL to generate a 100MHz clock.  The PHY will relock
      it, filter signal noise, and output the reference clock.  ASPM L0s
      works correctly, but circuit noise issues make it difficult to pass
      the TX compatibility test.

  (2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the
      PHY's PLL to generate 100MHz internally.  In this case, exit from
      ASPM L0s sometimes fails due to a design error in the RC receiver
      circuit.  Even if we use extended-synch, the PHY sometimes fails to
      relock the bits from FTS, which will hang the system.

We want the flexibility to use both clocking methods, so add a DT property,
"aspm-no-l0s".  If that's present, disable L0s to avoid the issues with
case (2).

[bhelgaas: changelog]
Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
2017-01-12 15:31:43 -06:00
Harunobu Kurokawa
e94888d237 PCI: rcar: Return -ENODEV from host bridge probe when no card present
R-Car PCIe does not support hotplug so it is appropriate to treat the
absence of a PCIe card as an -ENODEV error.

Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
[simon: updated changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-01-11 12:39:29 -06:00
Shawn Lin
013dd3d5e1 PCI: rockchip: Add system PM support
Add system PM support for Rockchip's RC.  For pre S3, the EP is configured
into D3 state which guarantees the link state should be in L1.  So we could
send PME_Turn_Off message to the EP and wait for its ACK to make the link
state into L2 or L3 without the aux-supply.  This could help save more
power which I think should be very important for mobile devices.

As note that there is a 5s timeout for RC to wait for the PMA_ACK after
sending PME_Turn_Off.  Technically it should depend on the hierarchy of
devices but seems PCIe core framework doesn't handle the L2/3 for S3 at
all.  So that means we should presume to set a default value for PME_ACK.
From the bug report[1], we could find a statement that Microsoft Windows
versions typically wait for 5 seconds.  So we are prone to take 5s for this
timeout here.

[1] https://lists.launchpad.net/kernel-packages/msg123315.html
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2017-01-11 12:22:47 -06:00
Murali Karicheri
a782b5f986 PCI: designware: Check for iATU unroll only on platforms that use ATU
Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT
even on platforms, e.g., Keystone, that do not have ATU ports.  This can
cause bad behavior such as asynchronous external aborts:

  OF: PCI:   MEM 0x60000000..0x6fffffff -> 0x60000000
  Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
  pgd = c0003000
  [00000000] *pgd=80000800004003, *pmd=00000000
  Internal error: : 1211 [#1] PREEMPT SMP ARM
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7
  Hardware name: Keystone
  task: eb878000 task.stack: eb866000
  PC is at dw_pcie_setup_rc+0x24/0x380
  LR is at ks_pcie_host_init+0x10/0x170

Move the dw_pcie_iatu_unroll_enabled() check so we only call it on
platforms that do not use the ATU.  These platforms supply their own
->rd_other_conf() and ->wr_other_conf() methods.

[bhelgaas: changelog]
Fixes: a0601a4705 ("PCI: designware: Add iATU Unroll feature")
Fixes: 416379f9eb ("PCI: designware: Check for iATU unroll support after initializing host")
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
CC: stable@vger.kernel.org	# v4.9+
2017-01-10 08:43:24 -06:00
Linus Torvalds
0ab7b12c49 pci-v4.10-changes
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Merge tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "PCI changes:

   - add support for PCI on ARM64 boxes with ACPI. We already had this
     for theoretical spec-compliant hardware; now we're adding quirks
     for the actual hardware (Cavium, HiSilicon, Qualcomm, X-Gene)

   - add runtime PM support for hotplug ports

   - enable runtime suspend for Intel UHCI that uses platform-specific
     wakeup signaling

   - add yet another host bridge registration interface. We hope this is
     extensible enough to subsume the others

   - expose device revision in sysfs for DRM

   - to avoid device conflicts, make sure any VF BAR updates are done
     before enabling the VF

   - avoid unnecessary link retrains for ASPM

   - allow INTx masking on Mellanox devices that support it

   - allow access to non-standard VPD for Chelsio devices

   - update Broadcom iProc support for PAXB v2, PAXC v2, inbound DMA,
     etc

   - update Rockchip support for max-link-speed

   - add NVIDIA Tegra210 support

   - add Layerscape LS1046a support

   - update R-Car compatibility strings

   - add Qualcomm MSM8996 support

   - remove some uninformative bootup messages"

* tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (115 commits)
  PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3)
  PCI: Expand "VPD access disabled" quirk message
  PCI: pciehp: Remove loading message
  PCI: hotplug: Remove hotplug core message
  PCI: Remove service driver load/unload messages
  PCI/AER: Log AER IRQ when claiming Root Port
  PCI/AER: Log errors with PCI device, not PCIe service device
  PCI/AER: Remove unused version macros
  PCI/PME: Log PME IRQ when claiming Root Port
  PCI/PME: Drop unused support for PMEs from Root Complex Event Collectors
  PCI: Move config space size macros to pci_regs.h
  x86/platform/intel-mid: Constify mid_pci_platform_pm
  PCI/ASPM: Don't retrain link if ASPM not possible
  PCI: iproc: Skip check for legacy IRQ on PAXC buses
  PCI: pciehp: Leave power indicator on when enabling already-enabled slot
  PCI: pciehp: Prioritize data-link event over presence detect
  PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar
  PCI: rcar: Use gen2 fallback compatibility last
  PCI: rcar-gen2: Use gen2 fallback compatibility last
  PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
  ..
2016-12-15 12:46:48 -08:00
Linus Torvalds
e71c3978d6 Merge branch 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull smp hotplug updates from Thomas Gleixner:
 "This is the final round of converting the notifier mess to the state
  machine. The removal of the notifiers and the related infrastructure
  will happen around rc1, as there are conversions outstanding in other
  trees.

  The whole exercise removed about 2000 lines of code in total and in
  course of the conversion several dozen bugs got fixed. The new
  mechanism allows to test almost every hotplug step standalone, so
  usage sites can exercise all transitions extensively.

  There is more room for improvement, like integrating all the
  pointlessly different architecture mechanisms of synchronizing,
  setting cpus online etc into the core code"

* 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (60 commits)
  tracing/rb: Init the CPU mask on allocation
  soc/fsl/qbman: Convert to hotplug state machine
  soc/fsl/qbman: Convert to hotplug state machine
  zram: Convert to hotplug state machine
  KVM/PPC/Book3S HV: Convert to hotplug state machine
  arm64/cpuinfo: Convert to hotplug state machine
  arm64/cpuinfo: Make hotplug notifier symmetric
  mm/compaction: Convert to hotplug state machine
  iommu/vt-d: Convert to hotplug state machine
  mm/zswap: Convert pool to hotplug state machine
  mm/zswap: Convert dst-mem to hotplug state machine
  mm/zsmalloc: Convert to hotplug state machine
  mm/vmstat: Convert to hotplug state machine
  mm/vmstat: Avoid on each online CPU loops
  mm/vmstat: Drop get_online_cpus() from init_cpu_node_state/vmstat_cpu_dead()
  tracing/rb: Convert to hotplug state machine
  oprofile/nmi timer: Convert to hotplug state machine
  net/iucv: Use explicit clean up labels in iucv_init()
  x86/pci/amd-bus: Convert to hotplug state machine
  x86/oprofile/nmi: Convert to hotplug state machine
  ...
2016-12-12 19:25:04 -08:00
Bjorn Helgaas
b08d2e61a6 Merge branch 'pci/host-vmd' into next
* pci/host-vmd:
  PCI: vmd: Fix suspend handlers defined-but-not-used warning
  PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU
  PCI: vmd: Remove unnecessary pci_set_drvdata()
2016-12-12 11:25:13 -06:00
Bjorn Helgaas
d34efd22ac Merge branch 'pci/host-tegra' into next
* pci/host-tegra:
  arm64: tegra: Enable PCIe on Jetson TX1
  arm64: tegra: Add PCIe host bridge on Tegra210
  PCI: tegra: Enable the driver on 64-bit ARM
  PCI: tegra: Add Tegra210 support
  PCI: tegra: Implement PCA enable workaround
  dt-bindings: pci: tegra: Add Tegra210 support
  PCI: tegra: Use new pci_register_host_bridge() interface
  PCI: Export host bridge registration interface
  PCI: Allow driver-specific data in host bridge
  PCI: Add pci_register_host_bridge() interface
2016-12-12 11:25:12 -06:00
Bjorn Helgaas
f77b3244c1 Merge branch 'pci/host-spear' into next
* pci/host-spear:
  PCI: spear: Use builtin_platform_driver() to simplify the code
2016-12-12 11:25:11 -06:00
Bjorn Helgaas
44b83b32e7 Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip:
  PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
  PCI: rockchip: Split out rockchip_cfg_atu()
  PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS
  PCI: rockchip: Correct the use of FTS mask
  PCI: rockchip: Remove the pointer to L1 substate cap
  PCI: rockchip: Specify the link capability
  PCI: rockchip: Fix negotiated lanes calculation
  PCI: rockchip: Add Kconfig COMPILE_TEST
  PCI: rockchip: Mark RC as common clock architecture
  PCI: rockchip: Provide captured slot power limit and scale
  PCI: rockchip: Add three new resets as required properties
  PCI: Don't attempt to claim shadow copies of ROM
  PCI: designware: Check for iATU unroll support after initializing host
  PCI: qcom: Fix pp->dev usage before assignment
  PCI: designware-plat: Update author email address
  PCI: layerscape: Fix drvdata usage before assignment
  PCI: designware-plat: Change maintainer to Jose Abreu
2016-12-12 11:25:11 -06:00
Bjorn Helgaas
a1d9190d96 Merge branch 'pci/host-rcar' into next
* pci/host-rcar:
  PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar
  PCI: rcar: Use gen2 fallback compatibility last
  PCI: rcar-gen2: Use gen2 fallback compatibility last
2016-12-12 11:25:10 -06:00
Bjorn Helgaas
aee10cd4c1 Merge branch 'pci/host-qcom' into next
* pci/host-qcom:
  PCI: qcom: Add support for MSM8996 PCIe controller
2016-12-12 11:25:10 -06:00
Bjorn Helgaas
46275d43c8 Merge branch 'pci/host-layerscape' into next
* pci/host-layerscape:
  PCI: layerscape: Add LS1046a support
  PCI: layerscape: Remove redundant error message from ls_pcie_probe()
2016-12-12 11:25:09 -06:00
Bjorn Helgaas
f887e24e05 Merge branch 'pci/host-iproc' into next
* pci/host-iproc:
  PCI: iproc: Skip check for legacy IRQ on PAXC buses
  PCI: iproc: Fix incorrect MSI address alignment
  PCI: iproc: Add support for the next-gen PAXB controller
  PCI: iproc: Add PAXBv2 binding info
  PCI: iproc: Add inbound DMA mapping support
  PCI: iproc: Add optional dma-ranges
  PCI: iproc: Make outbound mapping code more generic
  PCI: iproc: Remove redundant outbound properties
  PCI: iproc: Add PAXC v2 support
  PCI: iproc: Add PAXCv2 related binding
  PCI: iproc: Fix exception with multi-function devices
  PCI: iproc: Add BCMA type
  PCI: iproc: Do not reset PAXC when initializing the driver
  PCI: iproc: Improve core register population
2016-12-12 11:25:08 -06:00
Bjorn Helgaas
b0b8975906 Merge branch 'pci/host-hv' into next
* pci/host-hv:
  PCI: hv: Allocate physically contiguous hypercall params buffer
  PCI: hv: Delete the device earlier from hbus->children for hot-remove
  PCI: hv: Fix hv_pci_remove() for hot-remove
  PCI: hv: Use the correct buffer size in new_pcichild_device()
  PCI: hv: Make unnecessarily global IRQ masking functions static
2016-12-12 11:25:07 -06:00
Bjorn Helgaas
9fb7454b1d Merge branch 'pci/host-hisi' into next
* pci/host-hisi:
  PCI: hisi: Remove redundant error message from hisi_pcie_probe()
2016-12-12 11:25:07 -06:00
Bjorn Helgaas
a739d56dfb Merge branch 'pci/host-altera' into next
* pci/host-altera:
  PCI: altera: Remove redundant error message in altera_pcie_parse_dt()
  PCI: altera: Use builtin_platform_driver() to simplify the code
2016-12-12 11:25:06 -06:00
Bjorn Helgaas
2f0f3733c4 Merge branch 'pci/enumeration' into next
* pci/enumeration:
  PCI: Warn on possible RW1C corruption for sub-32 bit config writes
  PCI: Create revision file in sysfs
2016-12-12 11:25:02 -06:00
Andy Gospodarek
ffbd796821 PCI: iproc: Skip check for legacy IRQ on PAXC buses
PAXC and PAXCv2 buses do not support legacy IRQs so there is no reason to
even try and map them.  Without a change like this, one cannot create VFs
on Nitro ports since legacy interrupts are checked as part of the PCI
device creation process.  Testing on PAXC hardware showed that VFs are
properly created with only the change to not set pcie->map_irq, but just to
be safe the change in iproc_pcie_setup() will ensure that pdev_fixup_irq()
will not panic.

Signed-off-by: Andy Gospodarek <gospo@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
2016-12-08 12:24:20 -06:00
Simon Horman
49da21108f PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar
Add fallback compatibility string for the  R-Car Gen 3 family.  This is in
keeping with the both the existing fallback compatibility string for the
R-Car Gen 2 family and the fallback scheme being adopted wherever
appropriate for drivers for Renesas SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 16:56:56 -06:00
Simon Horman
d83a328ad1 PCI: rcar: Use gen2 fallback compatibility last
Improve readability by listing fallback compatibility strings after the
more-specific compatibility strings they provide a fallback for.

This does not affect run-time behaviour as it is the order in the DTB that
determines which compatibility string is used.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 16:56:38 -06:00
Simon Horman
7b99d94277 PCI: rcar-gen2: Use gen2 fallback compatibility last
Improve readability by listing fallback compatibility strings after the
more-specific compatibility strings they provide a fallback for.

This does not affect run-time behaviour as it is the order in the DTB that
determines which compatibility string is used.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 16:56:02 -06:00
Shawn Lin
0722bdd296 PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the
logic of reset control and reuse rockchip_pcie_init_port() later which
should fully follow the cold boot procedure of ROM code.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-07 15:08:25 -06:00
Shawn Lin
9e663d3f11 PCI: rockchip: Split out rockchip_cfg_atu()
Split out a new function, rockchip_cfg_atu(), in order to re-configure the
ATU when missing these information after wakeup from S3.

[bhelgaas: add "dev" temporary, return 0 when known]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-07 15:06:20 -06:00
Shawn Lin
f37500b8aa PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS
PCIE_RC_CONFIG_LCS contains control and status bits specific to the PCIe
link.  The layout for this register looks the same as the existing
PCI_EXP_LNKCTL and PCI_EXP_LNKSTA.  So let's reuse them.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:06:00 -06:00
Brian Norris
a45e2611b9 PCI: rockchip: Correct the use of FTS mask
We're trying to mask out bits[23:8] while retaining [32:24, 7:0], but we're
doing the inverse.  That doesn't have too much effect, since we're setting
all the [23:8] bits to 1, and the other bits are only relevant for modes
we're currently not using.  But we should get this right.

Fixes: ca19890840 ("PCI: rockchip: Fix wrong transmitted FTS count")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-12-07 15:06:00 -06:00
Shawn Lin
77bc68cf17 PCI: rockchip: Remove the pointer to L1 substate cap
Per the errata of TRM, the RC can't support L1 substate, so remove the L1
substate cap as well as operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.

Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
f2fb5b8f2a PCI: rockchip: Specify the link capability
rk3399 supports PCIe 2.x link speeds marginally at best, and on some
boards, the link won't train at 5 GT/s at all.  Rather than sacrifice 500ms
waiting for training that will never happen, let's use the helper function,
of_pci_get_max_link_speed(), to get the max link speed from DT and specify
link capability.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
45e9320f3a PCI: rockchip: Fix negotiated lanes calculation
The calculation of negotiated lanes is wrong: it should be shifted by
PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by
PCIE_CORE_PL_CONF_LANE_MASK instead.  Let's fix it.

Fixes: e77f847df5 ("PCI: rockchip: Add Rockchip PCIe controller support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
1177f76a7e PCI: rockchip: Add Kconfig COMPILE_TEST
Allow selection of the Rockchip driver for compile testing, even if we
aren't building for ARCH_ROCKCHIP.

[bhelgaas: changelog]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
b8ab8e041c PCI: rockchip: Mark RC as common clock architecture
The default value of common clock configuration is zero indicating
Rockchip's RC is using asynchronous clock architecture but actually we are
using common clock.  This will confuse some EP drivers if they need some
different settings referring to this value.

Set the Common Clock Configuration bit in the Link Control Register.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:58 -06:00
Shawn Lin
4816c4c7b8 PCI: rockchip: Provide captured slot power limit and scale
If vpcie3v3 is available, we could provide these information via RC's
configure register to make EP able to know the power limit.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:58 -06:00
Bjorn Helgaas
ca5ab37b19 PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy
Add Makefile comments to explain the Kconfig and build strategy for ARM64
drivers that work around not-quite-ECAM issues.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 14:34:58 -06:00
Geliang Tang
554d9ec7b4 PCI: spear: Use builtin_platform_driver() to simplify the code
Use builtin_platform_driver() helper to simplify the code.

Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 14:32:30 -06:00
Borislav Petkov
42db500a55 PCI: vmd: Fix suspend handlers defined-but-not-used warning
Fix the following warnings:

  drivers/pci/host/vmd.c:731:12: warning: ‘vmd_suspend’ defined but not used [-Wunused-function]
   static int vmd_suspend(struct device *dev)
              ^
  drivers/pci/host/vmd.c:739:12: warning: ‘vmd_resume’ defined but not used [-Wunused-function]
   static int vmd_resume(struct device *dev)
              ^

Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Reviewed-by: Keith Busch <keith.busch@intel.com>
2016-12-07 12:17:27 -06:00
Jon Derrick
3906b91844 PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU
SRCU lets synchronize_srcu() depend on VMD-local RCU primitives, preventing
long delays from locking up RCU in other systems.  VMD performs a
synchronize when removing a device, but will hit all IRQ lists if the
device uses all VMD vectors.  This patch will not help VMD's RCU
synchronization, but will isolate the read side delays to the VMD
subsystem.  Additionally, the use of SRCU in VMD's ISR will keep it
isolated from any other RCU waiters in the rest of the system.

Tested using concurrent FIO and NVMe resets:

  [global]
  rw=read
  bs=4k
  direct=1
  ioengine=libaio
  iodepth=32
  norandommap
  timeout=300
  runtime=1000000000

  [nvme0]
  cpus_allowed=0-63
  numjobs=8
  filename=/dev/nvme0n1

  [nvme1]
  cpus_allowed=0-63
  numjobs=8
  filename=/dev/nvme1n1

  while (true) do
    for i in /sys/class/nvme/nvme*; do
      echo "Resetting ${i##*/}"
      echo 1 > $i/reset_controller;
      sleep 5
    done;
  done

Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
2016-12-07 12:17:27 -06:00
Thierry Reding
7ac0271397 PCI: tegra: Enable the driver on 64-bit ARM
The Tegra PCI host controller driver no longer relies on any of the 32-bit
ARM glue for PCI, so it can be enabled on 64-bit configurations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07 12:07:05 -06:00
Thierry Reding
c7a091c762 PCI: tegra: Add Tegra210 support
The PCIe host controller found on Tegra X1 is very similar to its
predecessor on Tegra K1. A bug was introduced in the new revision that
is worked around by always enabling the performance counter, otherwise
accesses to configuration space will block for a number of seconds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07 12:06:42 -06:00
Thierry Reding
76245ca2df PCI: tegra: Implement PCA enable workaround
Tegra210's PCIe controller has a bug that requires the PCA (performance
counter) feature to be enabled. If this isn't done, accesses to device
configuration space will hang the chip for tens of seconds. Implement the
workaround.

Based on commit 514e19138af2 ("pci: tegra: implement PCA enable
workaround") from U-Boot by Stephen Warren <swarren@nvidia.com>.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07 12:06:33 -06:00
Arnd Bergmann
76f2541491 PCI: tegra: Use new pci_register_host_bridge() interface
Tegra is one of the remaining platforms that still use the traditional
pci_common_init_dev() interface for probing PCI host bridges.

This demonstrates how to convert it to the pci_register_host interface I
just added in a previous patch. This leads to a more linear probe sequence
that can handle errors better because we avoid callbacks into the driver,
and it makes the driver architecture independent.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07 12:06:17 -06:00
Duc Dang
c5d4603961 PCI: Add MCFG quirks for X-Gene host controller
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to
configure additional controller's register to address device at
bus:dev:function.

Add a quirk to discover controller MMIO register space and configure
controller registers to select and address the target secondary device.

The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).

Tested-by: Jon Masters <jcm@redhat.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06 13:45:50 -06:00
Tomasz Nowicki
648d93fc77 PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
ThunderX pass1.x requires to emulate the EA headers for on-chip devices
hence it has to use custom pci_thunder_ecam_ops for accessing PCI config
space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it
can be applied while probing ACPI based PCI host controller.

ThunderX pass1.x is using the same way for accessing off-chip devices
(so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries
too.

Quirk is considered for ThunderX silicon pass1.x only which is identified
via MCFG revision 2.

ThunderX pass 1.x requires the following accessors:

  NUMA node 0 PCI segments  0- 3: pci_thunder_ecam_ops (MCFG quirk)
  NUMA node 0 PCI segments  4- 9: thunder_pem_ecam_ops (MCFG quirk)
  NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk)
  NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)

[bhelgaas: change Makefile/ifdefs so quirk doesn't depend on
CONFIG_PCI_HOST_THUNDER_ECAM]
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06 13:45:50 -06:00
Tomasz Nowicki
44f22bd91e PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller
ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully
compliant with ECAM standard. It uses non-standard configuration space
accessors (see thunder_pem_ecam_ops) and custom configuration space
granulation (see bus_shift = 24). In order to access configuration space
and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk
infrastructure. This involves:
1. A new thunder_pem_acpi_init() init function to locate PEM-specific
   register ranges using ACPI.
2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk
   code.
3. New quirk entries for each PEM segment. Each contains platform IDs,
   mentioned thunder_pem_ecam_ops and CFG resources.

Quirk is considered for ThunderX silicon pass2.x only which is identified
via MCFG revision 1.

ThunderX pass 2.x requires the following accessors:

  NUMA Node 0 PCI segments  0- 3: pci_generic_ecam_ops (ECAM-compliant)
  NUMA Node 0 PCI segments  4- 9: thunder_pem_ecam_ops (MCFG quirk)
  NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant)
  NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)

[bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so
quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM]
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06 13:45:49 -06:00
Bjorn Helgaas
0d414268fb PCI: thunder-pem: Factor out resource lookup
Pull the register resource lookup out of thunder_pem_init() so we can
easily add a corresponding lookup using ACPI.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06 13:45:49 -06:00
Dongdong Liu
5f00f1a017 PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely
ECAM-compliant.  It is non-ECAM only for the RC bus config space; for any
other bus underneath the root bus it does support ECAM access.

Add specific quirks for PCI config space accessors.  This involves:
1. New initialization call hisi_pcie_init() to obtain RC base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

[bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't
depend on CONFIG_PCI_HISI]
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06 13:45:49 -06:00
Long Li
0de8ce3ee8 PCI: hv: Allocate physically contiguous hypercall params buffer
hv_do_hypercall() assumes that we pass a segment from a physically
contiguous buffer.  A buffer allocated on the stack may not work if
CONFIG_VMAP_STACK=y is set.

Use kmalloc() to allocate this buffer.

Reported-by: Haiyang Zhang <haiyangz@microsoft.com>
Signed-off-by: Long Li <longli@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2016-11-29 17:22:43 -06:00
Ray Jui
feacdb4a35 PCI: iproc: Fix incorrect MSI address alignment
In the code to handle PAXB v2 based MSI steering, the logic aligns the MSI
register address to the size of supported inbound mapping range.  This is
incorrect since it rounds "up" the starting address to the next aligned
address, but what we want is the starting address to be rounded "down" to
the aligned address.

This patch fixes the issue and allows MSI writes to be properly steered to
the GIC.

Fixes: 4b073155fbd3 ("PCI: iproc: Add support for the next-gen PAXB controller")
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-23 17:15:31 -06:00
Srinivas Kandagatla
d0491fc39b PCI: qcom: Add support for MSM8996 PCIe controller
Add support for the MSM8996/APQ8096 PCIe controller.  MSM8996 supports Gen
1/2, one lane, 3 PCIe root complexes with support for MSI and legacy
interrupts, and it conforms to PCI Express Base 2.1 specification.

Add a post_init callback to qcom_pcie_ops, as the PCIe pipe clocks are only
setup after the phy is powered on.  It also adds an ltssm_enable callback
as it is very much different from other supported SoCs in the driver.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2016-11-23 17:01:06 -06:00
Ray Jui
c7c44527b3 PCI: iproc: Add support for the next-gen PAXB controller
Add support for the next generation of the iProc PAXB host controller, used
in Stingray.

Signed-off-by: Oza Oza <oza.oza@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-23 16:51:14 -06:00
Sebastian Andrzej Siewior
9c248f8896 PCI/xgene-msi: Convert to hotplug state machine
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: linux-pci@vger.kernel.org
Cc: Duc Dang <dhdang@apm.com>
Cc: rt@linuxtronix.de
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20161117183541.8588-8-bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-11-22 23:34:40 +01:00
Bjorn Helgaas
fb26592301 PCI: Warn on possible RW1C corruption for sub-32 bit config writes
Hardware that supports only 32-bit config writes is not spec-compliant.
For example, if software performs a 16-bit write, we must do a 32-bit read,
merge in the 16 bits we intend to write, followed by a 32-bit write.  If
the 16 bits we *don't* intend to write happen to have any RW1C (write-one-
to-clear) bits set, we just inadvertently cleared something we shouldn't
have.

Add a rate-limited warning when we do sub-32 bit config writes.  Remove
similar probe-time warnings from some of the affected host bridge drivers.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Enthusiastically-Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>	# rockchip
Acked-by: Thierry Reding <treding@nvidia.com>
2016-11-21 16:25:39 -06:00
Ray Jui
dd9d4e7498 PCI: iproc: Add inbound DMA mapping support
Add support for inbound DMA mapping.  The range of the inbound mapping is
configured by the optional device tree property 'dma-ranges'.

While inbound mapping is done automatically in the ASIC on most iProc-based
SoCs, newer ASICs (e.g., Stingray) require inbound mapping to be configured
explicitly in software.

[bhelgaas: fold in fixes to avoid 32-bit division in iproc_pcie_ib_write()
and uninitialized return value in iproc_pcie_setup_ib() from Arnd Bergmann
<arnd@arndb.de>]
Signed-off-by: Oza Oza <oza.oza@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-17 14:40:37 -06:00
Ray Jui
4213e15c36 PCI: iproc: Make outbound mapping code more generic
Improve the iProc PCIe outbound mapping code by making it more generic and
removing redundant device tree properties 'brcm,pcie-ob-window-size' and
'brcm,pcie-ob-oarr-size'.  The driver is still backward compatible to
device tree binaries with the two properties specified.

The driver now automatically configures the correct mapping window size and
number of mapping windows based on the value of device tree property
'ranges' and the capability of of the iProc PCIe controller.

Signed-off-by: Oza Oza <oza.oza@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-17 14:40:37 -06:00
Ray Jui
787b3c4f2e PCI: iproc: Add PAXC v2 support
Add support for the second generation of the iProc PCIe PAXC host
controller.

Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-17 14:40:37 -06:00
Dexuan Cui
e74d2ebdda PCI: hv: Delete the device earlier from hbus->children for hot-remove
After we send a PCI_EJECTION_COMPLETE message to the host, the host will
immediately send us a PCI_BUS_RELATIONS message with
relations->device_count == 0, so pci_devices_present_work(), running on
another thread, can find the being-ejected device, mark the
hpdev->reported_missing to true, and run list_move_tail()/list_del() for
the device -- this races hv_eject_device_work() -> list_del().

Move the list_del() in hv_eject_device_work() to an earlier place, i.e.,
before we send PCI_EJECTION_COMPLETE, so later the
pci_devices_present_work() can't see the device.

Signed-off-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jake Oshins <jakeo@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
CC: Haiyang Zhang <haiyangz@microsoft.com>
CC: Vitaly Kuznetsov <vkuznets@redhat.com>
2016-11-16 16:46:44 -06:00
Dexuan Cui
17978524a6 PCI: hv: Fix hv_pci_remove() for hot-remove
1. We don't really need such a big on-stack buffer when sending the
teardown_packet: vmbus_sendpacket() here only uses sizeof(struct
pci_message).

2. In the hot-remove case (PCI_EJECT), after we send PCI_EJECTION_COMPLETE
to the host, the host will send a RESCIND_CHANNEL message to us and the
host won't access the per-channel ringbuffer any longer, so we needn't send
PCI_RESOURCES_RELEASED/PCI_BUS_D0EXIT to the host, and we shouldn't expect
the host's completion message of PCI_BUS_D0EXIT, which will never come.

3. We should send PCI_BUS_D0EXIT after hv_send_resources_released().

Signed-off-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jake Oshins <jakeo@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
CC: Haiyang Zhang <haiyangz@microsoft.com>
CC: Vitaly Kuznetsov <vkuznets@redhat.com>
2016-11-16 16:45:32 -06:00
Dexuan Cui
8286e96d95 PCI: hv: Use the correct buffer size in new_pcichild_device()
We don't really need such a big on-stack buffer.  vmbus_sendpacket() here
only uses sizeof(struct pci_child_message).

Signed-off-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jake Oshins <jakeo@microsoft.com>
2016-11-16 16:43:58 -06:00
Joao Pinto
9f46107b8c PCI: designware-plat: Update author email
I returned to Synopsys and so I am sending this patch to update the email
address of the pcie-designware-plat author.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-16 16:16:40 -06:00
Ray Jui
538928fd6c PCI: iproc: Fix exception with multi-function devices
During enumeration with multi-function EP devices, access to the
configuration space of a non-existent function results in an unsupported
request being returned as expected.  By default the PAXB-based iProc PCIe
controller forwards this as an APB error to the host system and that causes
an exception, which is undesired.

Disable this undesired behaviour and let the kernel PCI stack deal with an
access to the non-existent function, in which case a vendor ID of 0xffff is
returned and handled gracefully.

Reported-by: JD Zheng <jiandong.zheng@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Oza Oza <oza.oza@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-14 16:07:37 -06:00
Ray Jui
404349c5c8 PCI: iproc: Add BCMA type
The iProc PCIe driver is currently using type IPROC_PCIE_PAXB for the
following SoCs: NS, NSP, Cygnus, NS2, and Pegasus.  In fact, the BCMA-based
NS uses a legacy PAXB controller that is slightly different from the PAXB
controller used in the rest of SoCs, e.g., some registers are missing and
it does not require software configuration of outbound/inbound address
mapping.

Add a new type, IPROC_PCIE_PAXB_BCMA, to allow us to properly support the
BCMA-based NS along with other iProc-based SoCs going forward.

Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-14 15:55:33 -06:00
Ray Jui
7cbd50d275 PCI: iproc: Do not reset PAXC when initializing the driver
During initialization, the current iProc PCIe host driver resets PAXC and
the downstream internal endpoint device that PAXC connects to.  If the
endpoint device is already loaded with firmware and has started running
from the bootloader stage, this downstream reset causes the endpoint device
to stop working.

Signed-off-by: Ray Jui <raj.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-14 15:54:57 -06:00
Ray Jui
06324ede76 PCI: iproc: Improve core register population
As the number of iProc PCIe core registers starts to grow and differ
between different revisions of the iProc PCIe controllers, the
current way of populating each individual unsupported register with
value 'IPROC_PCIE_REG_INVALID' with a table entry has become a bit
messy and is difficult to scale up in the future.

Improve the current driver by populating the invalid entries with code
instead of through individual table entries.  This helps to avoid a
significant number of invalid table entries when support for the next
revision of the iProc controller is added.

Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-14 15:41:44 -06:00
Mingkai Hu
1d77040bde PCI: layerscape: Add LS1046a support
Add support for the LS1046a PCIe controller.  This device has a different
LUT_DBG offset, so add "lut_dbg" to ls_pcie_drvdata to
describe this difference.

[bhelgaas: changelog, remove now-unused PCIE_LUT_DBG]
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-11 16:40:16 -06:00
Wei Yongjun
5b23e8fa46 PCI: vmd: Remove unnecessary pci_set_drvdata()
The driver core clears the driver data to NULL after device_release or on
probe failure.  Thus, it is not needed to manually clear the device driver
data to NULL.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
2016-11-11 15:51:35 -06:00
Wei Yongjun
ad719956a8 PCI: hisi: Remove redundant error message from hisi_pcie_probe()
There is an error message from devm_ioremap_resource() already, so remove
the dev_err() call to avoid redundant error messages.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-11 15:42:40 -06:00
Wei Yongjun
e594233803 PCI: layerscape: Remove redundant error message from ls_pcie_probe()
There is an error message from devm_ioremap_resource() already, so remove
the dev_err() call to avoid redundant error messages.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-11 15:39:10 -06:00
Wei Yongjun
c19699a8c6 PCI: altera: Remove redundant error message in altera_pcie_parse_dt()
There is an error message from devm_ioremap_resource() already, so remove
the dev_err() call to avoid redundant error messages.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ley Foon Tan <lftan@altera.com>
2016-11-11 15:20:03 -06:00
Wei Yongjun
c5d933b122 PCI: altera: Use builtin_platform_driver() to simplify the code
Use the builtin_platform_driver() macro to make the code simpler.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-11 15:18:48 -06:00
Shawn Lin
31a3a7b5b2 PCI: rockchip: Add three new resets as required properties
pm_rst, aclk_rst, pclk_rst was controlled by ROM code so the software
wasn't needed to control it again in theory.  But it didn't work properly,
so we do need to do it again and add enough delay between the assert of
pm_rst and the deassert of pm_rst.  The Soc intergrated with this
controller, rk3399, is still under MP test internally, so the backward
compatibility won't be a big deal.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-11-10 11:14:37 -06:00
Niklas Cassel
416379f9eb PCI: designware: Check for iATU unroll support after initializing host
dw_pcie_iatu_unroll_enabled() reads a dbi_base register.  Reading any
dbi_base register before pp->ops->host_init has been called causes
"imprecise external abort" on platforms like ARTPEC-6, where the PCIe
module is disabled at boot and first enabled in pp->ops->host_init.  Move
dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after
pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used.

Fixes: a0601a4705 ("PCI: designware: Add iATU Unroll feature")
Tested-by: James Le Cuirot <chewi@gentoo.org>
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Olof Johansson <olof@lixom.net>
2016-11-04 15:28:55 -05:00
Tobias Klauser
542ccf4551 PCI: hv: Make unnecessarily global IRQ masking functions static
Make hv_irq_mask() and hv_irq_unmask() static as they are only used in
pci-hyperv.c

This fixes a sparse warning.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2016-10-31 13:22:42 -05:00
Srinivas Kandagatla
ad110449e2 PCI: qcom: Fix pp->dev usage before assignment
Initialize pp->dev in qcom_pcie_probe() before calling get_resources(),
which uses it.

[bhelgaas: changelog]
Fixes: e6a087eeaf ("PCI: qcom: Remove redundant struct qcom_pcie.dev")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-26 14:46:39 -05:00
Joao Pinto
02a1b8f416 PCI: designware-plat: Update author email address
Although I am leaving Synopsys, I would like to keep working with the linux
kernel community and help in what you might find useful.  For that I am
sending this patch to change my contact e-mail.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-21 09:54:46 -05:00
Marc Zyngier
15480f3ab7 PCI: layerscape: Fix drvdata usage before assignment
Commit fefe6733e5 ("PCI: layerscape: Move struct pcie_port setup
to probe function") changed the init ordering of the pcie structure,
but started to use the pcie->drvdata field before initializing it.
Mayhem follows.

Fix this by moving the drvdata assignment right before the first use.
Tested on LS2085a.

Fixes: efe6733e516 ("PCI: layerscape: Move struct pcie_port setup to probe function")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-17 07:58:18 -05:00
Linus Torvalds
40bd3a5f34 PCI changes for the v4.9 merge window:
Altera host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Remove redundant platform_get_resource() return value check (Bjorn Helgaas)
     Rename altera_pcie_valid_config() to altera_pcie_valid_device() (Bjorn Helgaas)
     Simplify TLB_CFG_DW0 usage (Bjorn Helgaas)
     Simplify TLP_CFG_DW1 usage (Bjorn Helgaas)
 
   APM X-Gene host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Pass struct xgene_pcie_port to setup functions (Bjorn Helgaas)
     Add register accessors (Bjorn Helgaas)
 
   Axis ARTPEC-6 host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Add register accessors (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Remove unnecessary artpec6_pcie_link_up() (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Add resource name comments (Bjorn Helgaas)
 
   Broadcom iProc host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Set drvdata at end of probe function (Bjorn Helgaas)
     Validate CSR base in BCMA setup code (Bjorn Helgaas)
     Remove redundant null pointer checking (Bjorn Helgaas)
     Hard-code PCIe capability offset instead of searching (Bjorn Helgaas)
 
   Freescale i.MX6 host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove redundant of_node pointer (Bjorn Helgaas)
     Removed unused struct imx6_pcie.mem_base (Bjorn Helgaas)
     Pass struct imx6_pcie to PHY accessors (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Reorder struct imx6_pcie (Bjorn Helgaas)
     Remove unused return values (Bjorn Helgaas)
 
   Freescale Layerscape host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Remove redundant struct ls_pcie.dbi (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Move struct pcie_port setup to probe function (Bjorn Helgaas)
     Remove unused ls_add_pcie_port() platform_device arg (Bjorn Helgaas)
     Reorder struct ls_pcie (Bjorn Helgaas)
 
   HiSilicon host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Name private struct pointer "hisi_pcie" consistently (Bjorn Helgaas)
     Remove redundant struct hisi_pcie.reg_base (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Include register block base in PCIE_SYS_STATE4 address (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Reorder struct hisi_pcie (Bjorn Helgaas)
 
   Marvell Aardvark host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     MAINTAINERS: Add DT binding to the Aardvark PCIe driver maintainer (Thomas Petazzoni)
 
   Marvell Armada host bridge driver
     Remove unused platform data (Bjorn Helgaas)
     Add local base pointer (Bjorn Helgaas)
     Remove redundant struct armada8k_pcie.base (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Reorder struct armada8k_pcie (Bjorn Helgaas)
     MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver (Thomas Petazzoni)
 
   Marvell MVEBU host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Use existing of_node pointer (Bjorn Helgaas)
 
   NVIDIA Tegra host bridge driver
     Fix argument order in tegra_pcie_phy_disable() (Bjorn Helgaas)
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
 
   Qualcomm host bridge driver
     Remove unused platform data (Bjorn Helgaas)
     Remove redundant struct qcom_pcie.dbi (Bjorn Helgaas)
     Remove redundant struct qcom_pcie.dev (Bjorn Helgaas)
     Reorder struct qcom_pcie (Bjorn Helgaas)
 
   Renesas R-Car host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Remove unused rcar_pcie_get_resources() platform_device arg (Bjorn Helgaas)
     Remove DRV_NAME macro (Bjorn Helgaas)
     rcar-gen2: Add local struct device pointers (Bjorn Helgaas)
 
   Rockchip host bridge driver
     Remove unused platform data (Bjorn Helgaas)
     Indent "if" statement body (Dan Carpenter)
 
   Samsung Exynos host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Uninline register accessors (Bjorn Helgaas)
     Name private struct pointer "exynos_pcie" consistently (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Reorder struct exynos_pcie (Bjorn Helgaas)
 
   ST Microelectronics SPEAr13xx host bridge driver
     Remove unused constants (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Reorder struct spear13xx_pcie (Bjorn Helgaas)
     Clean up struct device usage (Bjorn Helgaas)
 
   Synopsys DesignWare host bridge driver
     Rename dw_pcie_valid_config() to dw_pcie_valid_device() (Bjorn Helgaas)
     Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces (Bjorn Helgaas)
     Swap order of dw_pcie_writel_rc() reg/val arguments (Bjorn Helgaas)
     Export dw_pcie_readl_rc(), dw_pcie_writel_rc() (Bjorn Helgaas)
     Uninline register accessors (Bjorn Helgaas)
     Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() (Kishon Vijay Abraham I)
     Swap order of dw_pcie_writel_unroll() reg/val arguments (Bjorn Helgaas)
     designware-plat: Remove redundant dw_plat_pcie.mem_base (Bjorn Helgaas)
     designware-plat: Add local struct device pointers (Bjorn Helgaas)
     designware-plat: Remove unused platform data (Bjorn Helgaas)
 
   TI DRA7xx host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove redundant struct device pointer from dra7xx_pcie (Bjorn Helgaas)
     Set drvdata at end of probe function (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Pass device-specific struct to internal functions (Bjorn Helgaas)
     Move struct pcie_port setup to probe function (Bjorn Helgaas)
     Reorder struct dra7xx_pcie (Bjorn Helgaas)
 
   TI Keystone host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Use generic DesignWare accessors (Bjorn Helgaas)
     Pass keystone_pcie, not address, to IRQ functions (Bjorn Helgaas)
     Pass keystone_pcie, not va_app_base, to DBI functions (Bjorn Helgaas)
     Add app register accessors (Bjorn Helgaas)
     Reorder struct keystone_pcie (Bjorn Helgaas)
 
   Xilinx AXI host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
     Removed unused xilinx_pcie_assign_msi() argument (Bjorn Helgaas)
 
   Xilinx NWL host bridge driver
     Add local struct device pointers (Bjorn Helgaas)
     Remove unused platform data (Bjorn Helgaas)
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Merge tag 'pci-v4.9-changes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

PCI changes for the v4.9 merge window:
 "Here are some more changes I'd like to have in v4.9.  There's one
  small Tegra bug fix in the PHY poweroff path, which is only used in
  failure paths.

  The rest is all strictly cleanup that should make host bridge drivers
  more readable, but shouldn't actually change any behavior.

  Summary:

   - use local struct device pointers in many host bridge drivers for
     clarity

   - remove unused platform data

   - use generic DesignWare accessors

   - misc cleanups: remove redundant structure entries and re-order
     structure members to put comon generic fields first etc"

* tag 'pci-v4.9-changes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (108 commits)
  MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver
  MAINTAINERS: Add DT binding to the Aardvark PCIe driver maintainer
  PCI: rockchip: Indent "if" statement body
  PCI: hisi: Reorder struct hisi_pcie
  PCI: hisi: Pass device-specific struct to internal functions
  PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
  PCI: dra7xx: Reorder struct dra7xx_pcie
  PCI: xilinx-nwl: Remove unused platform data
  PCI: xilinx-nwl: Add local struct device pointers
  PCI: xilinx: Removed unused xilinx_pcie_assign_msi() argument
  PCI: xilinx: Remove unused platform data
  PCI: xilinx: Add local struct device pointers
  PCI: xgene: Add register accessors
  PCI: xgene: Pass struct xgene_pcie_port to setup functions
  PCI: xgene: Remove unused platform data
  PCI: tegra: Remove unused platform data
  PCI: tegra: Add local struct device pointers
  PCI: tegra: Fix argument order in tegra_pcie_phy_disable()
  PCI: rockchip: Remove unused platform data
  PCI: rcar-gen2: Add local struct device pointers
  ...
2016-10-13 17:08:58 -07:00
Bjorn Helgaas
217c6d21e9 Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx', 'pci/host-exynos', 'pci/host-hisi', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-qcom' and 'pci/host-spear' into next
* pci/host-armada:
  MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver
  PCI: armada: Reorder struct armada8k_pcie
  PCI: armada: Pass device-specific struct to internal functions
  PCI: armada: Use generic DesignWare accessors
  PCI: armada: Remove redundant struct armada8k_pcie.base
  PCI: armada: Add local base pointer
  PCI: armada: Remove unused platform data

* pci/host-artpec:
  PCI: artpec6: Add resource name comments
  PCI: artpec6: Pass device-specific struct to internal functions
  PCI: artpec6: Remove unnecessary artpec6_pcie_link_up()
  PCI: artpec6: Use generic DesignWare accessors
  PCI: artpec6: Add register accessors
  PCI: artpec6: Remove unused platform data
  PCI: artpec6: Add local struct device pointers

* pci/host-dra7xx:
  PCI: dra7xx: Reorder struct dra7xx_pcie
  PCI: dra7xx: Move struct pcie_port setup to probe function
  PCI: dra7xx: Pass device-specific struct to internal functions
  PCI: dra7xx: Use generic DesignWare accessors
  PCI: dra7xx: Set drvdata at end of probe function
  PCI: dra7xx: Remove redundant struct device pointer from dra7xx_pcie
  PCI: dra7xx: Add local struct device pointers

* pci/host-exynos:
  PCI: exynos: Reorder struct exynos_pcie
  PCI: exynos: Pass device-specific struct to internal functions
  PCI: exynos: Name private struct pointer "exynos_pcie" consistently
  PCI: exynos: Uninline register accessors
  PCI: exynos: Add local struct device pointers

* pci/host-hisi:
  PCI: hisi: Reorder struct hisi_pcie
  PCI: hisi: Pass device-specific struct to internal functions
  PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
  PCI: hisi: Use generic DesignWare accessors
  PCI: hisi: Remove redundant struct hisi_pcie.reg_base
  PCI: hisi: Name private struct pointer "hisi_pcie" consistently
  PCI: hisi: Remove unused platform data
  PCI: hisi: Add local struct device pointers

* pci/host-imx6:
  PCI: imx6: Remove unused return values
  PCI: imx6: Reorder struct imx6_pcie
  PCI: imx6: Use generic DesignWare accessors
  PCI: imx6: Pass device-specific struct to internal functions
  PCI: imx6: Pass struct imx6_pcie to PHY accessors
  PCI: imx6: Removed unused struct imx6_pcie.mem_base
  PCI: imx6: Remove redundant of_node pointer
  PCI: imx6: Add local struct device pointers

* pci/host-keystone:
  PCI: keystone: Reorder struct keystone_pcie
  PCI: keystone: Add app register accessors
  PCI: keystone: Pass keystone_pcie, not va_app_base, to DBI functions
  PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
  PCI: keystone: Use generic DesignWare accessors
  PCI: keystone: Add local struct device pointers

* pci/host-layerscape:
  PCI: layerscape: Reorder struct ls_pcie
  PCI: layerscape: Remove unused ls_add_pcie_port() platform_device arg
  PCI: layerscape: Move struct pcie_port setup to probe function
  PCI: layerscape: Pass device-specific struct to internal functions
  PCI: layerscape: Remove redundant struct ls_pcie.dbi
  PCI: layerscape: Remove unused platform data
  PCI: layerscape: Add local struct device pointers

* pci/host-qcom:
  PCI: qcom: Reorder struct qcom_pcie
  PCI: qcom: Remove redundant struct qcom_pcie.dev
  PCI: qcom: Remove redundant struct qcom_pcie.dbi
  PCI: qcom: Remove unused platform data

* pci/host-spear:
  PCI: spear: Clean up struct device usage
  PCI: spear: Reorder struct spear13xx_pcie
  PCI: spear: Pass device-specific struct to internal functions
  PCI: spear: Remove unused constants
2016-10-12 11:15:06 -05:00
Bjorn Helgaas
22c7e1d4b4 Merge branch 'pci/host-designware' into next
* pci/host-designware:
  PCI: designware-plat: Remove unused platform data
  PCI: designware-plat: Add local struct device pointers
  PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base
  PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments
  PCI: designware: Uninline register accessors
  PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()
  PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
  PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces
  PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()
  PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()
2016-10-12 11:14:58 -05:00
Bjorn Helgaas
dd5bba52d3 Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-iproc', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-rockchip', 'pci/host-tegra', 'pci/host-xgene' and 'pci/host-xilinx' into next
* pci/host-aardvark:
  MAINTAINERS: Add DT binding to the Aardvark PCIe driver maintainer
  PCI: aardvark: Remove unused platform data
  PCI: aardvark: Add local struct device pointers

* pci/host-altera:
  PCI: altera: Simplify TLP_CFG_DW1 usage
  PCI: altera: Simplify TLB_CFG_DW0 usage
  PCI: altera: Rename altera_pcie_valid_config() to altera_pcie_valid_device()
  PCI: altera: Remove redundant platform_get_resource() return value check
  PCI: altera: Remove unused platform data
  PCI: altera: Add local struct device pointers

* pci/host-iproc:
  PCI: iproc: Hard-code PCIe capability offset instead of searching
  PCI: iproc: Remove redundant null pointer checking
  PCI: iproc: Validate CSR base in BCMA setup code
  PCI: iproc: Set drvdata at end of probe function
  PCI: iproc: Add local struct device pointers

* pci/host-mvebu:
  PCI: mvebu: Use existing of_node pointer
  PCI: mvebu: Add local struct device pointers

* pci/host-rcar:
  PCI: rcar-gen2: Add local struct device pointers
  PCI: rcar: Remove DRV_NAME macro
  PCI: rcar: Remove unused rcar_pcie_get_resources() platform_device arg
  PCI: rcar: Remove unused platform data
  PCI: rcar: Add local struct device pointers

* pci/host-rockchip:
  PCI: rockchip: Indent "if" statement body
  PCI: rockchip: Remove unused platform data

* pci/host-tegra:
  PCI: tegra: Remove unused platform data
  PCI: tegra: Add local struct device pointers
  PCI: tegra: Fix argument order in tegra_pcie_phy_disable()

* pci/host-xgene:
  PCI: xgene: Add register accessors
  PCI: xgene: Pass struct xgene_pcie_port to setup functions
  PCI: xgene: Remove unused platform data
  PCI: xgene: Add local struct device pointers

* pci/host-xilinx:
  PCI: xilinx-nwl: Remove unused platform data
  PCI: xilinx-nwl: Add local struct device pointers
  PCI: xilinx: Removed unused xilinx_pcie_assign_msi() argument
  PCI: xilinx: Remove unused platform data
  PCI: xilinx: Add local struct device pointers
2016-10-12 11:14:44 -05:00
Dan Carpenter
08015ee0ff PCI: rockchip: Indent "if" statement body
Body of an "if" statement wasn't indented.  Add a tab.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 07:14:09 -05:00
Bjorn Helgaas
f84cfdf721 PCI: hisi: Reorder struct hisi_pcie
Reorder struct hisi_pcie to put generic fields first.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:08:32 -05:00
Bjorn Helgaas
e9480b5a7f PCI: hisi: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:08:27 -05:00
Bjorn Helgaas
a458ce33d4 PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
Include the PCIE_HIP06_CTRL_OFF block base in the PCIE_SYS_STATE4 register
address so reads of PCIE_SYS_STATE4 don't have to mention both.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:08:25 -05:00
Bjorn Helgaas
8e5ec4143d PCI: dra7xx: Reorder struct dra7xx_pcie
Reorder struct dra7xx_pcie to put generic fields first.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:05:54 -05:00
Bjorn Helgaas
228ee66c46 PCI: xilinx-nwl: Remove unused platform data
The xilinx-nwl driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:00:51 -05:00
Bjorn Helgaas
adf9e284b4 PCI: xilinx-nwl: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:00:30 -05:00
Bjorn Helgaas
e59e5ff9a0 PCI: xilinx: Removed unused xilinx_pcie_assign_msi() argument
xilinx_pcie_assign_msi() doesn't use the struct xilinx_pcie_port pointer
passed to it, so remove the argument completely.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 00:00:00 -05:00
Bjorn Helgaas
6a6c2e8a7c PCI: xilinx: Remove unused platform data
The xilinx driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:59:51 -05:00
Bjorn Helgaas
5d07188e21 PCI: xilinx: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:59:44 -05:00
Bjorn Helgaas
8e93c5132c PCI: xgene: Add register accessors
Add device-specific register accessors for consistency across host drivers.
No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:54:31 -05:00
Bjorn Helgaas
4ecf6b0f83 PCI: xgene: Pass struct xgene_pcie_port to setup functions
Pass the struct xgene_pcie_port pointer, not addresses, to setup functions.
This enables future simplifications.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:49:52 -05:00
Bjorn Helgaas
c6fe9ebaac PCI: xgene: Remove unused platform data
The xgene driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:48:33 -05:00
Bjorn Helgaas
16cbff1407 PCI: tegra: Remove unused platform data
The tegra driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:45:32 -05:00
Bjorn Helgaas
a581fa9936 PCI: tegra: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:45:25 -05:00
Bjorn Helgaas
8dd99bca7b PCI: tegra: Fix argument order in tegra_pcie_phy_disable()
The tegra_pcie_phy_disable() path called pads_writel() with arguments in
the wrong order.  Swap them to be the "value, offset" order expected by
pads_writel().

Fixes: 6fe7c187e0 ("PCI: tegra: Support per-lane PHYs")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
CC: stable@vger.kernel.org	# v4.7+
2016-10-11 23:45:24 -05:00
Bjorn Helgaas
9d274755c6 PCI: rockchip: Remove unused platform data
The rockchip driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-10-11 23:38:10 -05:00
Bjorn Helgaas
de9e6bc84b PCI: rcar-gen2: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-11 23:34:57 -05:00
Bjorn Helgaas
3ff8e4ac3a PCI: rcar: Remove DRV_NAME macro
The DRV_NAME macro is only used once, so there's no real advantage to
having the macro at all.  Remove it and use the "rcar-pcie" name directly
in the struct platform_driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-11 23:34:49 -05:00
Bjorn Helgaas
d0206f2121 PCI: rcar: Remove unused rcar_pcie_get_resources() platform_device arg
rcar_pcie_get_resources() doesn't use the platform_device pointer passed to
it, so remove it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-11 23:34:34 -05:00
Bjorn Helgaas
d9c64c500a PCI: rcar: Remove unused platform data
The rcar driver never uses the platform drvdata pointer, so don't bother
setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-11 23:34:28 -05:00
Bjorn Helgaas
ee05369412 PCI: qcom: Reorder struct qcom_pcie
Reorder struct qcom_pcie to put generic fields first.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:27:46 -05:00
Bjorn Helgaas
e6a087eeaf PCI: qcom: Remove redundant struct qcom_pcie.dev
Remove the struct qcom_pcie.dev member, which is a duplicate of the generic
pp.dev member.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:26:02 -05:00
Bjorn Helgaas
0edd578e7a PCI: qcom: Remove redundant struct qcom_pcie.dbi
Remove the struct qcom_pcie.dbi member, which is a duplicate of the generic
pp.dbi_base member.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:23:15 -05:00
Bjorn Helgaas
661a0e4ce0 PCI: qcom: Remove unused platform data
The qcom driver never uses the platform drvdata pointer, so don't bother
setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:22:45 -05:00
Bjorn Helgaas
96f61707f2 PCI: mvebu: Use existing of_node pointer
Use the existing "np" pointer instead of looking up dev->of_node again.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:19:05 -05:00
Bjorn Helgaas
160b4e4189 PCI: mvebu: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:16:46 -05:00
Bjorn Helgaas
6caaa28d92 PCI: layerscape: Reorder struct ls_pcie
Reorder struct ls_pcie to put generic fields first.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:15:58 -05:00
Bjorn Helgaas
4726a8231e PCI: layerscape: Remove unused ls_add_pcie_port() platform_device arg
ls_add_pcie_port() doesn't use the platform_device pointer passed to it, so
remove it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:14:46 -05:00
Bjorn Helgaas
fefe6733e5 PCI: layerscape: Move struct pcie_port setup to probe function
Do the basic pcie_port setup in the probe function for consistency with
other drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:14:29 -05:00
Bjorn Helgaas
7b0b11133c PCI: layerscape: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:14:25 -05:00
Bjorn Helgaas
d41d295959 PCI: layerscape: Remove redundant struct ls_pcie.dbi
Remove the struct ls_pcie.dbi member, which is a duplicate of the generic
pp.dbi_base member.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:14:22 -05:00
Bjorn Helgaas
9f6a148f82 PCI: layerscape: Remove unused platform data
The layerscape driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 23:13:24 -05:00
Bjorn Helgaas
c11125ebe7 PCI: layerscape: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:59:55 -05:00
Bjorn Helgaas
4841f3ad0c PCI: keystone: Reorder struct keystone_pcie
Reorder struct keystone_pcie to put generic fields first.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:58:43 -05:00
Bjorn Helgaas
5c725353e1 PCI: keystone: Add app register accessors
Add device-specific register accessors for consistency across host drivers.
No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:58:34 -05:00
Bjorn Helgaas
e481e0d00d PCI: keystone: Pass keystone_pcie, not va_app_base, to DBI functions
Instead of passing ks_pcie->va_app_base to DBI mode functions,
pass the struct keystone_pcie.  This will allow them to use register
accessors.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:56:55 -05:00
Bjorn Helgaas
5649e4ced9 PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
Instead of passing the application register base to IRQ functions,
pass the struct keystone_pcie.  This will allow them to use register
accessors.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:56:46 -05:00
Bjorn Helgaas
f3eca6c4f4 PCI: keystone: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the keystone
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:54:54 -05:00
Bjorn Helgaas
21fa0c51f0 PCI: keystone: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:53:22 -05:00
Bjorn Helgaas
e3a1698b1e PCI: iproc: Hard-code PCIe capability offset instead of searching
We know where the PCIe capability lives in the host bridge's config space;
in fact, we already hard-coded the offset of the Link Control 2 register.

The hard-coded Link Control 2 offset was 0xdc.  Link Control 2 is at offset
0x30 into the PCIe capability, so the capability itself must be at
0xdc - 0x30 = 0xac.

Hard-code the PCIe capability offset, which means we don't have to search
for it and we can use the standard definitions for registers within the
capability.

No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:44:22 -05:00
Bjorn Helgaas
6d76833c52 PCI: iproc: Remove redundant null pointer checking
The callers never pass a null "pcie" pointer (they check for kzalloc
failure), so we don't need to check here.  The bus driver should never call
the probe function with a null ->dev pointer, so we don't need to check
that either.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:41:07 -05:00
Bjorn Helgaas
f66e5b2907 PCI: iproc: Validate CSR base in BCMA setup code
Validate iproc_pcie->base for BCMA devices just like we already do for
platform devices in iproc_pcie_pltfm_probe().  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:38:51 -05:00
Bjorn Helgaas
556c7bb7df PCI: iproc: Set drvdata at end of probe function
Set the drvdata pointer at the end of probe function for consistency with
other drivers.  We don't need the drvdata until after the probe completes,
and we don't need it at all if the probe fails.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:36:38 -05:00
Bjorn Helgaas
786aeccb4a PCI: iproc: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:28:01 -05:00
Bjorn Helgaas
9ab021b6cf PCI: imx6: Remove unused return values
Remove unused return values.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:26:28 -05:00
Bjorn Helgaas
916bf1cc65 PCI: imx6: Reorder struct imx6_pcie
Reorder struct imx6_pcie to put generic fields first.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:26:28 -05:00
Bjorn Helgaas
2a6a85d536 PCI: imx6: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the imx6
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:26:28 -05:00
Bjorn Helgaas
e7d7705ace PCI: imx6: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:26:28 -05:00
Bjorn Helgaas
8bad7f2fc3 PCI: imx6: Pass struct imx6_pcie to PHY accessors
Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors.
This enables future simplifications.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:09:32 -05:00
Bjorn Helgaas
51c84709b8 PCI: imx6: Removed unused struct imx6_pcie.mem_base
Removed the unused struct imx6_pcie.mem_base member.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:03:40 -05:00
Bjorn Helgaas
c5af40747c PCI: imx6: Remove redundant of_node pointer
"np" and "node" are redundant copies of the of_node pointer.  Remove "np"
and use "node" instead.  Replace the "fsl,max-link-speed" use with "node"
as well.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 22:00:50 -05:00
Bjorn Helgaas
13957652f7 PCI: imx6: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:54:51 -05:00
Bjorn Helgaas
4368f096c4 PCI: hisi: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the hisi
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:45:19 -05:00
Bjorn Helgaas
761c43c735 PCI: hisi: Remove redundant struct hisi_pcie.reg_base
Remove the struct hisi_pcie.reg_base member, which is a duplicate of the
generic pp.dbi_base member.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:43:12 -05:00
Bjorn Helgaas
bf4ed37cbb PCI: hisi: Name private struct pointer "hisi_pcie" consistently
Most struct hisi_pcie pointers are already called "hisi_pcie".  Change
the rest of them to match.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:40:32 -05:00
Bjorn Helgaas
d5d4f6e423 PCI: hisi: Remove unused platform data
The hisi driver never uses the platform drvdata pointer, so don't bother
setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:38:45 -05:00
Bjorn Helgaas
88790f99c7 PCI: hisi: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:32:09 -05:00
Bjorn Helgaas
6b1f185a5f PCI: exynos: Reorder struct exynos_pcie
Reorder struct exynos_pcie to put generic fields first.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:30:52 -05:00
Bjorn Helgaas
cc08e82b85 PCI: exynos: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:26:39 -05:00
Bjorn Helgaas
10284bfa34 PCI: exynos: Name private struct pointer "exynos_pcie" consistently
Most struct exynos_pcie pointers are already called "exynos_pcie".  Change
the rest of them to match.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:24:29 -05:00
Bjorn Helgaas
53e5bff16f PCI: exynos: Uninline register accessors
The register accessors are not performance critical and are small enough
that the compiler can inline them itself if it makes sense.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:24:12 -05:00
Bjorn Helgaas
fae68d690d PCI: exynos: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:18:59 -05:00
Bjorn Helgaas
150645b943 PCI: dra7xx: Move struct pcie_port setup to probe function
Do the basic pcie_port setup in the probe function for consistency with
other drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:14:30 -05:00
Bjorn Helgaas
21baa1c498 PCI: dra7xx: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:09:14 -05:00
Bjorn Helgaas
feeb720180 PCI: dra7xx: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the dra7xx
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:04:27 -05:00
Bjorn Helgaas
03fa2ae184 PCI: dra7xx: Set drvdata at end of probe function
Set the drvdata pointer at the end of probe function for consistency with
other drivers.  We don't need the drvdata until after the probe completes,
and we don't need it at all if the probe fails.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 21:02:00 -05:00
Bjorn Helgaas
01856d1de4 PCI: dra7xx: Remove redundant struct device pointer from dra7xx_pcie
The DesignWare core already stores the struct device pointer in struct
pcie_port.  Remove the redundant copy from struct dra7xx_pcie.dev.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 20:59:39 -05:00
Bjorn Helgaas
c7f8146b7c PCI: dra7xx: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 20:50:57 -05:00
Bjorn Helgaas
7c62efcfc6 PCI: artpec6: Add resource name comments
Add comments about the Device Tree source of resources.  No functional
change.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:49:40 -05:00
Bjorn Helgaas
b6f5f434f0 PCI: artpec6: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:49:33 -05:00
Bjorn Helgaas
acaa88e4e2 PCI: artpec6: Remove unnecessary artpec6_pcie_link_up()
Remove artpec6_pcie_link_up(); the generic dw_pcie_link_up() does the same
thing, so we don't need a device-specific version.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:49:23 -05:00
Bjorn Helgaas
0d93f8d17e PCI: artpec6: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the armada8k
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:48:39 -05:00
Bjorn Helgaas
26fbcc5a45 PCI: artpec6: Add register accessors
Add device-specific register accessors for consistency across host
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:46:22 -05:00
Bjorn Helgaas
f392bd11e6 PCI: artpec6: Remove unused platform data
The artpec6 driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:45:31 -05:00
Bjorn Helgaas
e6f3115f58 PCI: artpec6: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2016-10-11 20:41:35 -05:00
Bjorn Helgaas
a477815f89 PCI: armada: Reorder struct armada8k_pcie
Reorder the device-specific struct to put the DesignWare generic struct
pcie_port first.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 20:33:01 -05:00
Bjorn Helgaas
b2d6fd77d7 PCI: armada: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 20:29:21 -05:00
Bjorn Helgaas
76876957ef PCI: armada: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the armada8k
driver.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 20:26:29 -05:00
Bjorn Helgaas
74e69079e2 PCI: armada: Remove redundant struct armada8k_pcie.base
The struct armada8k_pcie.base pointer is always a constant offset from
struct pcie_port.dbi_base.  Encode that offset in the register macros so we
don't need to maintain the armada8k_pcie.base pointer.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 20:26:17 -05:00
Bjorn Helgaas
afb374f8ac PCI: armada: Add local base pointer
Add a local "base" pointer, as is done for other uses, to simplify a
subsequent patch.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 20:11:23 -05:00
Bjorn Helgaas
e4aea9c4ad PCI: armada: Remove unused platform data
The armada driver never uses the platform drvdata pointer, so don't bother
setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 20:03:22 -05:00
Bjorn Helgaas
4f27628861 PCI: altera: Simplify TLP_CFG_DW1 usage
TLP_CFG_DW1() was only used with altera->root_bus_nr and RP_DEVFN, so
encode that directly into the macro so we don't have to clutter the uses
with the TLP_REQ_ID() usage.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:57:49 -05:00
Bjorn Helgaas
eb5767122f PCI: altera: Simplify TLB_CFG_DW0 usage
All TLP_CFG_DW0() uses follow the same pattern based on the root bus
number, so pull that into the macro itself to declutter the users.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:56:01 -05:00
Bjorn Helgaas
14c7b9580f PCI: altera: Rename altera_pcie_valid_config() to altera_pcie_valid_device()
Rename altera_pcie_valid_config() to altera_pcie_valid_device().
No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:54:38 -05:00
Bjorn Helgaas
dbeb4bd8ba PCI: altera: Remove redundant platform_get_resource() return value check
devm_ioremap_resource() fails gracefully when given a NULL resource
pointer, so we don't need to check separately for failure from
platform_get_resource_byname().  Remove the redundant check.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:54:23 -05:00
Bjorn Helgaas
ee34264eec PCI: altera: Remove unused platform data
The altera driver never uses the platform drvdata pointer, so don't bother
setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:54:22 -05:00
Bjorn Helgaas
fe4906778c PCI: altera: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 19:50:52 -05:00
Bjorn Helgaas
f2ab1bbaf5 PCI: aardvark: Remove unused platform data
The aardvark driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 19:44:04 -05:00
Bjorn Helgaas
9aec2feaf7 PCI: aardvark: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-10-11 19:38:03 -05:00
Bjorn Helgaas
6a43a425a0 PCI: spear: Clean up struct device usage
For consistency with other drivers, use the struct device pointer from
struct pcie_port whenever possible instead of relying on the
platform_device pointer.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:45:47 -05:00
Bjorn Helgaas
7a29f04a56 PCI: spear: Reorder struct spear13xx_pcie
Reorder struct spear13xx_pcie to put generic fields first.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:45:47 -05:00
Bjorn Helgaas
ffe82fa66a PCI: spear: Pass device-specific struct to internal functions
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:45:47 -05:00
Bjorn Helgaas
ca7b941c90 PCI: spear: Remove unused constants
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:45:47 -05:00
Bjorn Helgaas
4c9441d1e6 PCI: designware-plat: Remove unused platform data
The designware-plat driver never uses the platform drvdata pointer, so
don't bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:38:46 -05:00
Bjorn Helgaas
2d6054b968 PCI: designware-plat: Add local struct device pointers
Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:38:46 -05:00
Bjorn Helgaas
bb8a794777 PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base
Remove the struct dw_plat_pcie.mem_base member, which is only used as a
temporary.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:38:44 -05:00
Bjorn Helgaas
f5acb5c51d PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments
Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:34:47 -05:00
Bjorn Helgaas
3d469939bc PCI: designware: Uninline register accessors
The register accessors are not performance critical and small enough that
the compiler can inline them itself if it makes sense.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:33:58 -05:00
Bjorn Helgaas
8ad7501934 PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()
Export dw_pcie_readl_rc() and dw_pcie_writel_rc().  Many other drivers can
use these instead of implementing their own versions.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:31:52 -05:00
Bjorn Helgaas
ad88021894 PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers.  No functional
change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:30:33 -05:00
Bjorn Helgaas
7e00dfd0fb PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces
The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.

Make the signature of the override functions the same as the default
accessors.  This makes the default dw_pcie_readl_rc() and the corresponding
override more structurally similar: both will compute the final register
address with "pp->dbi_base + reg".  Previously dw_pcie_readl_rc() computed
the address and passed it to the override.

No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:29:25 -05:00
Kishon Vijay Abraham I
a26e0108b6 PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()
dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what
dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them
directly.

[bhelgaas: reworked into patch series]
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-11 08:26:21 -05:00