Commit Graph

166 Commits

Author SHA1 Message Date
Ben Skeggs
d5f423947a drm/nouveau: rename nouveau_vram to nouveau_mem
This structure will also be used for GART in the near future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:45:55 +10:00
Ben Skeggs
3425df486c drm/nv50-nvc0: unmap buffers from the vm when they're evicted
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:45:49 +10:00
Ben Skeggs
db5c8e299a drm/nv50-nvc0: restrict memtype to those specified at creation time
Upcoming patches are going to enable full support for buffers that keep
a constant GPU virtual address whenever they're validated for use by
the GPU.

In order for this to work properly while keeping support for large pages,
we need to know if it's ever going to be possible for a buffer to end
up in GART, and if so, disable large pages for the buffer's VMA.

This is a new restriction that's not present in earlier kernel's, but
should not break userspace as the current code never attempts to validate
buffers into a memtype other than it was created with.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:45:43 +10:00
Ben Skeggs
6ba9a68317 drm/nouveau: pass domain rather than ttm flags to gem_new()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:45:40 +10:00
Ben Skeggs
d550c41e4f drm/nouveau: remove no_vm/mappable flags from nouveau_bo
'mappable' isn't really used at all, nor is it necessary anymore as the
bo code is capable of moving buffers to mappable vram as required.

'no_vm' isn't necessary anymore either, any places that don't want to be
mapped into a GPU address space should allocate the VRAM directly instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:45:34 +10:00
Ben Skeggs
f13e435c59 drm/nv50-nvc0: switch to tasklet for display isr bh
We need to be able to have the bh run while possibly spinning waiting for
the EVO notifier to signal.  This apparently happens in some circumstances
with preempt disabled, so our workqueue was never being run.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:44:59 +10:00
Ben Skeggs
ef8389a84b drm/nv50-nvc0: move non-sharable display state into private structure
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:44:39 +10:00
Tejun Heo
d82f8e6c80 drm/nouveau: use system_wq instead of dev_priv->wq
With cmwq, there's no reason for nouveau to use a dedicated workqueue.
Drop dev_priv->wq and use system_wq instead.  Each work item is sync
flushed when the containing structure is unregistered/destroyed.

Note that this change also makes sure that nv50_gpio_handler is not
freed while the contained work item is still running.

Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:44:36 +10:00
Ben Skeggs
7948758d27 drm/nv40: implement support for on-chip PCIEGART
v2. moved nv44 pciegart table back to instmem, where it's not
    accessible by userspace clients.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:44:04 +10:00
Ben Skeggs
58e6c7a918 drm/nouveau: introduce new gart type, and name _SGDMA more appropriately
In preparation for the addition of a new nv40 backend, we'll need to be
able to distinguish between a paged dma object and the on-chip GART.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-02-25 06:30:15 +10:00
Dave Airlie
52bb4a7391 Merge branch 'drm-nouveau-next' of git://git.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
* 'drm-nouveau-next' of git://git.freedesktop.org/git/nouveau/linux-2.6:
  drm/nvc0/grctx: correct an off-by-one
  drm/nv50: Fix race with PFIFO during PGRAPH context destruction.
  drm/nouveau: Workaround incorrect DCB entry on a GeForce3 Ti 200.
  drm/nvc0: implement irq handler for whatever's at 0x14xxxx
  drm/nvc0: fix incorrect TPC register setup
  drm/nouveau: probe for adt7473 before f75375
  drm/nouveau: remove dead function definition
2011-01-26 17:12:42 +10:00
Ben Skeggs
1c2a679aa9 drm/nouveau: remove dead function definition
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-01-25 11:04:30 +10:00
Dave Airlie
51fda92223 Merge remote branch 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next into drm-fixes
* 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next:
  drm/nouveau: fix gpu page faults triggered by plymouthd
  drm/nouveau: greatly simplify mm, killing some bugs in the process
  drm/nvc0: enable protection of system-use-only structures in vm
  drm/nv40: initialise 0x17xx on all chipsets that have it
  drm/nv40: make detection of 0x4097-ful chipsets available everywhere
2011-01-17 12:20:31 +10:00
Ben Skeggs
c906ca0fbf drm/nvc0: enable protection of system-use-only structures in vm
Somehow missed this in the original merge of the nvc0 code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-01-17 11:28:50 +10:00
Ben Skeggs
c693931d93 drm/nv40: make detection of 0x4097-ful chipsets available everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-01-17 11:28:31 +10:00
Dave Airlie
7ad7f87b87 Merge remote branch 'nouveau/drm-nouveau-next' of ../drm-nouveau-next into drm-core-next
* 'nouveau/drm-nouveau-next' of ../drm-nouveau-next:
  drm/nouveau: fix hwmon device binding
  drm/nouveau: create grctx on the fly on all chipsets
  drm/nvc0: fix init without firmware present
  drm/nvc0/pgraph: fix 0x406028/0x405870 init
  drm/nvc0/pgraph: more unit names
  drm/nvc0/pfifo: support for chipsets with only one PSUBFIFO (0xc1)
  drm/nvc0: reserve only subc 0 for kernel use
  drm/nv50: sync up gr data error names with rnn, use for nvc0 also
  drm/nvc0: parse a couple more PGRAPH_INTR
  drm/nvc0: nuke left-over debug messages
  drm/nvc0: kill off a couple more magics
  drm/nouveau: Validate channel indices passed from userspace.
  drm/nouveau: Only select ACPI_VIDEO if its dependencies are met
2011-01-10 09:23:49 +10:00
Dave Airlie
5bcf719b7d drm/switcheroo: track state of switch in drivers.
We need to track the state of the switch in drivers, so that after s/r
we don't resume the card we've explicitly switched off before. Also
don't allow a userspace open to occur if we've switched the gpu off.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-05 13:45:30 +10:00
Ben Skeggs
6effe39364 drm/nv50: sync up gr data error names with rnn, use for nvc0 also
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-30 11:48:03 +10:00
Ben Skeggs
966a5b7daa drm/nvc0: implement pgraph engine hooks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-21 17:18:32 +10:00
Ben Skeggs
b2b099388f drm/nvc0: implement pfifo engine hooks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-21 17:17:39 +10:00
Ben Skeggs
8984e04615 drm/nvc0: initial vm implementation, use for bar1/bar3 management
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-21 17:17:14 +10:00
Ben Skeggs
4c74eb7ff2 drm/nvc0: import initial vm backend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-21 17:17:09 +10:00
Francisco Jerez
fd70b6cd78 drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 15:53:04 +10:00
Ben Skeggs
60d2a88ae8 drm/nouveau: kick vram functions out into an "engine"
NVC0 will be able to share some of nv50's paths this way.  This also makes
it the card-specific vram code responsible for deciding if a given set
of tile_flags is valid, rather than duplicating the allowed types in
nv50_vram.c and nouveau_gem.c

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:20 +10:00
Ben Skeggs
34cf01bc4b drm/nouveau: allow gpuobj vinst to be a virtual address when necessary
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:19 +10:00
Ben Skeggs
b571fe21f5 drm/nv50: tidy up PCIEGART implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:17 +10:00
Ben Skeggs
4c13614298 drm/nv50: implement global channel address space on new VM code
As of this commit, it's guaranteed that if an object is in VRAM that its
GPU virtual address will be constant.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:13 +10:00
Ben Skeggs
f869ef8823 drm/nv50: implement BAR1/BAR3 management on top of new VM code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:12 +10:00
Ben Skeggs
a11c3198c9 drm/nv50: import new vm code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:10 +10:00
Ben Skeggs
573a2a37e8 drm/nv50: implement custom vram mm
This is required on nv50 as we need to be able to have more precise control
over physical VRAM allocations to avoid buffer corruption when using
buffers of mixed memory types.

This removes some nasty overallocation/alignment that we were previously
using to "control" this problem.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 13:48:07 +10:00
Ben Skeggs
7a45d764a8 drm/nouveau: wrap calls to ttm_bo_validate()
This will be used later to fixup bo.offset with a buffer's fixed GPU
virtual address.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 03:00:37 +01:00
Ben Skeggs
12fb952507 drm/nouveau: introduce a util function to wait on reg != val
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 03:00:36 +01:00
Ben Skeggs
ceac30999d drm/nouveau: implicitly insert non-DMA objects into RAMHT
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 03:00:35 +01:00
Francisco Jerez
6dccd311dd drm/nouveau: Synchronize with the user channel before GPU object destruction.
There have been reports of PFIFO cache errors during context take down
(fdo bug 31637). They are caused by some GPU objects being taken out
while the channel is still potentially processing commands. Make sure
that all the previous rendering has landed before releasing a GPU
object.

Reported-by: Grzesiek Sójka <pld@pfu.pl>
Reported-by: Patrice Mandin <patmandin@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08 03:00:23 +01:00
Ben Skeggs
7f4a195fcb drm/nouveau: tidy up and extend dma object creation interfaces
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:59 +10:00
Ben Skeggs
7b4808bb6e drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present instead
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:54 +10:00
Ben Skeggs
20f63afe98 drm/nv50: allocate page for unknown PFB object in nv50_fb.c
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:50 +10:00
Ben Skeggs
e41115d0ad drm/nouveau: rework gpu-specific instmem interfaces
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:48 +10:00
Ben Skeggs
dc1e5c0dbf drm/nouveau: simplify gpuobj suspend/resume
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:47 +10:00
Ben Skeggs
fce2bad0ee drm/nv50: rework PGPIO IRQ handling and hotplug detection
Allows callers to install their own handlers for when a GPIO line
changes state (such as for hotplug detect).

This also fixes a bug where we weren't acknowledging the GPIO IRQ
until after the bottom half had run, causing a severe IRQ storm
in some cases.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:45 +10:00
Ben Skeggs
274fec93cd drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c files
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:41 +10:00
Ben Skeggs
5178d40dff drm/nouveau: move PFIFO ISR into nv04_fifo.c
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:39 +10:00
Ben Skeggs
2cbd4c8185 drm/nv50: move GPIO ISR to nv50_gpio.c
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:32 +10:00
Ben Skeggs
8f8a54482b drm/nouveau: allow irq handlers to be installed by engine-specific code
Lets start to clean up this mess!

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:29 +10:00
Francisco Jerez
87a326a385 drm/nv20: Add Z compression support.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Xavier Chantry <chantry.xavier@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:21 +10:00
Francisco Jerez
a5cf68b04b drm/nouveau: Rework tile region handling.
The point is to share more code between the PFB/PGRAPH tile region
hooks, and give the hardware specific functions a chance to allocate
per-region resources.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:20 +10:00
Francisco Jerez
e419cf0954 drm/nouveau: Add a separate class for the kernel channel mutex.
nouveau_bo_move_m2mf() needs to lock the kernel channel, and it may be
called from the pushbuf IOCTL with an user channel already locked. Use
a separate subclass for the kernel channel mutex because this is
legitimate mutex nesting.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:18 +10:00
Francisco Jerez
1f6d2de2c5 drm/nv50: Keep track of the head a channel is vsync'ing to.
In a multihead setup vblank interrupts may end up enabled in both
heads. In that case we want to ignore the vblank interrupts coming
from the wrong CRTC to avoid tearing and unbalanced calls to
drm_vblank_get/put (fdo bug 31074).

Reported-by: Felix Leimbach <felix.leimbach@gmx.net>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:16 +10:00
Francisco Jerez
332b242f47 drm/nouveau: Implement the pageflip ioctl.
nv0x-nv4x should be mostly fine, nv50 doesn't work yet.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:12 +10:00
Francisco Jerez
042206c0cd drm/nouveau: Implement the vblank DRM hooks.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03 15:11:11 +10:00