Commit Graph

10 Commits

Author SHA1 Message Date
Linus Torvalds
f66477a0ae The majority of the changes are driver updates and new device
support. The core framework is mostly unchanged this time
 around, with only a couple patches to expose a clk provider
 API and make getting clk parent names from DT more robust.
 
 Driver updates:
 
 - Support for clock controllers found on Broadcom Northstar
   SoCs and bcm2835 SoC
 
 - Support for Allwinner audio clocks
 
 - A few cleanup patches for Tegra drivers and support for the
   highest DFLL frequencies on Tegra124
 
 - Samsung exynos7 fixes and improvements
 
 - i.Mx SoC updates to add a few missing clocks and keep debug
   uart clocks on during kernel intialization
 
 - Some mediatek cleanups and support for more subsystem clocks
 
 - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
   controllers
 
 - A new driver for the Silabs si514 clock chip
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABCAAGBQJWOov3AAoJENidgRMleOc9qF4P/Rj/Gw/E0dyjE1fE3j4V9iNJ
 YJere7Zzr1ueG2THfMk335JGN7hQQkP8ofe8QzS4Opbo0m/Y+RxWo++1PDLUytxv
 wu79HGFKNCEXqqWvIfm30cgoZ59sjjHpVaZHgDDL17YEG2GxWlzstjKXp/E3EDer
 UOW75sKQ5E9AoWiqySmzZSUunWrgwOBoCA6OR9JhBRa5rzXisu1inIOw8K+zw1q1
 WtOekpricaodajIsI+2dFTtAokBOqRsrhcBptYI9ZpZtqVMc+wVWjHqEQHzEkLC0
 q4VMVUspt+/dnI3zjM5KkOe553A8wXqehuIek6y0osdwDtCgwAcU/dL9e27MmqvE
 0jbJ+vu1UlHkFsSaxYxEQKvQONqVEAPOFomW+9qabF/pMNiXloBVEGCKpV8R8HtB
 NyJvOcdTFouESGvFntvn6MV5GHFveFiRWRKacq+9QVvitEsu6Xg7mP4kTh0hf1C6
 zb1o3s1Z1iGnWcEjAPTNBHEte17mkR9magxkoyB4GzaNxempWHyZ+MXLEiTgQyjA
 MMTROM1Lg4aftPaASBtMvL//YHSXAd0P924I2KKTTf1X+yP60XLLSVrdMvPgTXy1
 bV1L7Vszo1BMVYbFD9YG+pGnXFzia2NJafQoLgw+Cm3Mo2ApqjCdtj/UADFT+/Bz
 X0ZKA7w9nUM+rD2EMSi1
 =K6iN
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The majority of the changes are driver updates and new device support.
  The core framework is mostly unchanged this time around, with only a
  couple patches to expose a clk provider API and make getting clk
  parent names from DT more robust.

  Driver updates:

   - Support for clock controllers found on Broadcom Northstar SoCs and
     bcm2835 SoC

   - Support for Allwinner audio clocks

   - A few cleanup patches for Tegra drivers and support for the highest
     DFLL frequencies on Tegra124

   - Samsung exynos7 fixes and improvements

   - i.Mx SoC updates to add a few missing clocks and keep debug uart
     clocks on during kernel intialization

   - Some mediatek cleanups and support for more subsystem clocks

   - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
     controllers

   - A new driver for the Silabs si514 clock chip"

* tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits)
  clk: qcom: msm8960: Fix dsi1/2 halt bits
  clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks
  clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks
  clk: Add clk_hw_is_enabled() for use by clk providers
  clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n
  clk: versatile-icst: fix memory leak
  clk: Remove clk_{register,unregister}_multiplier()
  clk: iproc: define Broadcom NS2 iProc clock binding
  clk: iproc: define Broadcom NSP iProc clock binding
  clk: ns2: add clock support for Broadcom Northstar 2 SoC
  clk: iproc: Separate status and control variables
  clk: iproc: Split off dig_filter
  clk: iproc: Add PLL base write function
  clk: nsp: add clock support for Broadcom Northstar Plus SoC
  clk: iproc: Add PWRCTRL support
  clk: cygnus: Convert all macros to all caps
  ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
  clk: imx31: add missing of_node_put
  clk: imx27: add missing of_node_put
  clk: si5351: add missing of_node_put
  ...
2015-11-05 12:59:36 -08:00
Douglas Anderson
4351f19a33 clk: rockchip: Make calculations use rounding
Let's use DIV_ROUND_CLOSEST for rounding, not just truncating
division.  This lets us get closer to the right rate.

Before this:
  set_phase(86) delay_nums=26 reg[0xf000420c]=0x468 actual_degrees=83
  set_phase(89) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86

After this:
  set_phase(86) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86
  set_phase(89) delay_nums=28 reg[0xf000420c]=0x470 actual_degrees=90

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:07 +01:00
Douglas Anderson
f0232063fb clk: rockchip: Allow more precision for some mmc clock phases
Because of the inexact nature of the extra MMC delay elements (it's
not possible to keep the phase monotonic and to also make phases (mod
90) > 70), we previously only allowed phases (mod 90) of 22.5, 45,
and 67.5.

But it's not the end of the world if the MMC clock phase goes
non-monotonic.  At most we'll be 25 degrees off.  It's way better to
test more phases to look for bad ones than to be 25 degrees off, because
in the case of MMC really the point is to find bad phases and get as far
asway from the as possible.  If we get to test extra phases by going
slightly non-monotonic then that might be fine.  Worst case we would
end up at a phases that's slight differnt than the one we wanted, but
at least we'd still be quite far away from the a bad phase.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Fold in more precise variance-values of 44-77 instead of 40-80.
Fold in the actual removal of the monotonic requirement and adapt
patch message accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26 16:00:06 +01:00
Shawn Lin
7a03fe6f48 clk: rockchip: reset init state before mmc card initialization
mmc host controller's IO input/output timing is unpredictable if
bootloader execute tuning for HS200 mode. It might make kernel failed
to initialize mmc card in identification mode. The root cause is
tuning phase and degree setting for HS200 mode in bootloader aren't
applicable to that of identification mode in kernel stage. Anyway, we
can't force all bootloaders to reset tuning phase and degree setting
before into kernel. Simply reset it in rockchip_clk_register_mmc.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01 16:36:54 -07:00
Stephen Boyd
836ee0f7d9 clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:12 -07:00
Stephen Boyd
9cfad9bc47 Merge branch 'cleanup-clk-h-includes' into clk-next
* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...
2015-07-28 11:59:09 -07:00
Stephen Boyd
f684ff8b67 clk: rockchip: Properly include clk.h
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h if it's actually used.

Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:10 -07:00
Heiko Stuebner
7c494ad058 clk: rockchip: fix issues in the mmc-phase clock
The review for the new inverter clock type uncovered some issues (missing
headers and name handling) that are also present in the mmc-phase clock
type, I got (to much) inspiration from. Fix these there too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06 15:07:38 -07:00
Uwe Kleine-König
4a1caed3d0 clk: make several parent names const
Since commit 2893c37946 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04 14:27:06 -07:00
Alexandru M Stan
89bf26cbc1 clk: rockchip: Add support for the mmc clock phases using the framework
This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).

The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.

There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28 00:44:24 +01:00