Commit Graph

7 Commits

Author SHA1 Message Date
Maxime Ripard
d312f6fb80 ARM: sunxi: Remove useless allwinner,drive property
The allwinner,drive property set to 10mA was really considered as our
default. Remove all those properties entirely to make that obvious.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-26 08:24:50 +01:00
Maxime Ripard
15df8ad971 ARM: gr8: Add UART3 pins
The UART3 pins were missing from the DTSI. Add them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22 15:32:10 +01:00
Maxime Ripard
7c432442c8 ARM: gr8: Add UART2 pins
The UART2 pins were missing from the DTSI. Add them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22 15:32:10 +01:00
Maxime Ripard
aade6b90d5 ARM: gr8: Add missing pwm channel 1 pin
The PWM controller has two different channels, but only the first pin was
exposed in the DTSI. Add the other one.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22 15:32:09 +01:00
Maxime Ripard
e900146c2f ARM: gr8: Fix typo in the i2s mclk pin group
There was a dumb copy and paste mistake here, fix it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22 15:32:09 +01:00
Maxime Ripard
95f4b4f444 ARM: gr8: Add the UART3
The GR8 has access to the UART3 controller, which was missing in the
DTSI. Add it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22 15:32:08 +01:00
Maxime Ripard
e5cd7ff705 ARM: gr8: Rename the DTSI and relevant DTS
Reviews have found that sun5i was a better prefix after all for the GR8.
Rename the relevant device trees before it's too late.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-22 15:06:04 +01:00