Commit Graph

27 Commits

Author SHA1 Message Date
Ben Skeggs
27740383dd drm/nva3/pm: initial attempt at more magic PFB regs
The reg calculation may get moved elsewhere at some point, but lets
figure out what exactly we need to do first.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24 16:31:16 +10:00
Ben Skeggs
8d7bb40063 drm/nouveau/pm: rework to allow selecting separate profiles for ac/battery
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13 17:09:04 +10:00
Ben Skeggs
a9bc247cbb drm/nouveau/pm: detect when we need dll disabled for gddr3
Fixes minor flickering on NVS295 when at perflvl 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13 17:08:54 +10:00
Ben Skeggs
2d85bc8855 drm/nouveau/pm: introduce ram reclocking helper
This will probably result in more lines of code, however, we're going to
have at least 3 slightly different implementations of this very soon and
I'd rather keep the ram reclocking logic separate from the hw specifics.

DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13 17:08:13 +10:00
Ben Skeggs
fd99fd6100 drm/nouveau/pm: calculate memory timings at perflvl creation time
Statically generating the PFB register and MR values for each timing set
turns out to be insufficient.  There's at least one (so far) known piece
of information which effects MR values which is stored in the perflvl
entry on some chipsets (and in another table on later ones), which is
disconnected from the timing table entries.

After this change we will generate a timing set based on an input clock
frequency instead, and have this data stored in the performance level
data.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13 17:08:03 +10:00
Ben Skeggs
045da4e555 drm/nvc0/pm: initial engine reclocking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:46 +10:00
Ben Skeggs
675aac033e drm/nouveau: just pass gpio line to pwm_*, not entire gpio struct
We don't need more than the line id to determine the PWM controller, and
the GPIO interfaces are about to change somewhat.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:44 +10:00
Ben Skeggs
36f1317ed0 drm/nv04-nv30/pm: port to newer interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:24 +10:00
Ben Skeggs
f3fbaf34e2 drm/nv50/pm: rewrite clock management, and switch to the new pm hooks
This area is horrifically complicated on these chipsets, and it's likely we
will need at least a few more tweaks yet.

Oh yes, and it's completely disabled on IGPs for the moment.  From traces,
things look potentially different there yet again.  Sigh...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:24 +10:00
Martin Peres
dd1da8de17 drm/nouveau/pm: make clocks_set return an error code clocks_set can fail.
Reporting an error is better than silently refusing to reclock.

V2: Use the same logic on nv40

Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:23 +10:00
Ben Skeggs
6934618014 drm/nv40/pm: convert to new pwm hooks, also fixing pwm type detection
A NV49 appeared a while back that was using the "nv41 style" pwm registers,
rather than the "nv40 style" ones my board is using.  This disproves the
previous theory that the pwm controller choice is chipset-specific.

So, after looking at a bunch of vbios images it appears that the next viable
theory is that we should select the pwm controller to use based on the gpio
line the fan is tied to, just like we do on nv50.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:13 +10:00
Ben Skeggs
5a4267ab14 drm/nv50/pm: convert to new fanspeed pwm controller hooks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:12 +10:00
Ben Skeggs
cb9fa62671 drm/nv50/pm: add support for pwm fan control
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:11 +10:00
Ben Skeggs
04de6a0461 drm/nv41/pm: implement a second type of fanspeed pwm
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:10 +10:00
Ben Skeggs
9232969e19 drm/nv40/pm: implement first type of pwm fanspeed funcs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:09 +10:00
Ben Skeggs
1262a206da drm/nv40/pm: write nv40-specific reclocking routines
Not 100% perfect yet, but a good start towards what it'll look like in the
end.

Actually seems stable on a NV44 I have here, as much as running around OA
for a fair amount of time constantly switching between performance levels
can prove..

My NV49 isn't quite so happy, and semaphores mess up somehow (sometimes) as
a result of the memory reclocking.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:10:45 +10:00
Ben Skeggs
354d0781e5 drm/nvc0/pm: initial implementation of clocks_get()
Not too certain on memory clock yet, but it gets the right numbers for
each perflvl on my NVC0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:03:16 +10:00
Ben Skeggs
ca94a71fc4 drm/nva3/pm: rewrite clock_set, and switch to new interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:01:51 +10:00
Ben Skeggs
fade7ad56d drm/nva3: split pm backend out from nv50
This will end up quite different, it makes sense for it to be completely
separate.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:54 +10:00
Ben Skeggs
5c6dc65754 drm/nouveau: pass perflvl struct to clock_pre()
On certain boards, there's BIOS scripts and memory timings that need to
be modified with the memclk.  Just pass in the entire perflvl struct and
let the chipset-specific code decide what to do.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:41 +10:00
Roy Spliet
7760fcb020 drm/nouveau: Import initial memory timing work
This isn't correct everywhere yet, but since we don't use the data yet
it's perfectly safe to push in, and the information we gain from logs
will help to fix the remaining issues.

v2 (Ben Skeggs <bskeggs@redhat.com>):
- fixed up formatting
- free parsed timing info on takedown
- switched timing table printout to debug loglevel

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:32 +10:00
Francisco Jerez
8155cac489 drm/nouveau: Refactor nouveau_temp_get() into engine pointers.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:29:29 +10:00
Martin Peres
34e9d85a1a drm/nouveau: Add temperature support (vbios parsing, readings, hwmon)
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:28:28 +10:00
Ben Skeggs
64f1c11a47 drm/nouveau: restore perflvl on resume, and restore boot perflvl on unload
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:35 +10:00
Ben Skeggs
442b626ece drm/nv04-nv40: import initial pm backend
Currently just hooked up to the already-existing nouveau_hw, which should
handle all relevant chipsets as well as we currently can.

This will likely be eventually split out and improved into chipset specific
code at a later point.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:13 +10:00
Ben Skeggs
02c30ca0a1 drm/nv50: import initial clock get/set routines + hook up pm engine
This will make nouveau_pm attempt to report the card's current performance
level both during bootup, and through sysfs.

This is a very initial implementation, and can be improved a *lot*

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:06 +10:00
Ben Skeggs
330c5988ee drm/nouveau: import initial work on vbios performance table parsing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:00 +10:00