The BF526-EZBRD changed SDRAM chips between board revisions, so create a
timing table that can accommodate both.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We defined SDRAM_tRAS to TRAS_4, but then wrongly defined SDRAM_tRAS_num
to 3.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data
path width, typically set 0 for a 32-bit bus width. On other
Blackfin derivatives this bit should be set by default.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove duplicated code and headers
- add option allowing arbitrary SDRAM/DDR Timing parameters.
- mark automatically calculated timings as EXPERIMENTAL
- fix comment header block
Related to BUGs:
- kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on.
- kernel does not boot if re-program clocks
[ Mike Frysinger <vapier.adi@gmail.com>
- fix comment header
- mark do_sync static
- document the DMA shutdown
- simplify SIC_IWR handling
- fix ANOMALY_05000265 handling to work as intended ]
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
