Remove the restart handler from "mach-lpc32xx";
this functionality is now available in the
pnx4008 watchdog driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Remove the restart hook assignment from phy3250;
this functionality is now managed by
the pnx4008 watchdog driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
but lots of architecture-specific changes.
* ARM:
- VHE support so that we can run the kernel at EL2 on ARMv8.1 systems
- PMU support for guests
- 32bit world switch rewritten in C
- various optimizations to the vgic save/restore code.
* PPC:
- enabled KVM-VFIO integration ("VFIO device")
- optimizations to speed up IPIs between vcpus
- in-kernel handling of IOMMU hypercalls
- support for dynamic DMA windows (DDW).
* s390:
- provide the floating point registers via sync regs;
- separated instruction vs. data accesses
- dirty log improvements for huge guests
- bugfixes and documentation improvements.
* x86:
- Hyper-V VMBus hypercall userspace exit
- alternative implementation of lowest-priority interrupts using vector
hashing (for better VT-d posted interrupt support)
- fixed guest debugging with nested virtualizations
- improved interrupt tracking in the in-kernel IOAPIC
- generic infrastructure for tracking writes to guest memory---currently
its only use is to speedup the legacy shadow paging (pre-EPT) case, but
in the future it will be used for virtual GPUs as well
- much cleanup (LAPIC, kvmclock, MMU, PIT), including ubsan fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQEcBAABAgAGBQJW5r3BAAoJEL/70l94x66D2pMH/jTSWWwdTUJMctrDjPVzKzG0
yOzHW5vSLFoFlwEOY2VpslnXzn5TUVmCAfrdmFNmQcSw6hGb3K/xA/ZX/KLwWhyb
oZpr123ycahga+3q/ht/dFUBCCyWeIVMdsLSFwpobEBzPL0pMgc9joLgdUC6UpWX
tmN0LoCAeS7spC4TTiTTpw3gZ/L+aB0B6CXhOMjldb9q/2CsgaGyoVvKA199nk9o
Ngu7ImDt7l/x1VJX4/6E/17VHuwqAdUrrnbqerB/2oJ5ixsZsHMGzxQ3sHCmvyJx
WG5L00ubB1oAJAs9fBg58Y/MdiWX99XqFhdEfxq4foZEiQuCyxygVvq3JwZTxII=
=OUZZ
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini:
"One of the largest releases for KVM... Hardly any generic
changes, but lots of architecture-specific updates.
ARM:
- VHE support so that we can run the kernel at EL2 on ARMv8.1 systems
- PMU support for guests
- 32bit world switch rewritten in C
- various optimizations to the vgic save/restore code.
PPC:
- enabled KVM-VFIO integration ("VFIO device")
- optimizations to speed up IPIs between vcpus
- in-kernel handling of IOMMU hypercalls
- support for dynamic DMA windows (DDW).
s390:
- provide the floating point registers via sync regs;
- separated instruction vs. data accesses
- dirty log improvements for huge guests
- bugfixes and documentation improvements.
x86:
- Hyper-V VMBus hypercall userspace exit
- alternative implementation of lowest-priority interrupts using
vector hashing (for better VT-d posted interrupt support)
- fixed guest debugging with nested virtualizations
- improved interrupt tracking in the in-kernel IOAPIC
- generic infrastructure for tracking writes to guest
memory - currently its only use is to speedup the legacy shadow
paging (pre-EPT) case, but in the future it will be used for
virtual GPUs as well
- much cleanup (LAPIC, kvmclock, MMU, PIT), including ubsan fixes"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (217 commits)
KVM: x86: remove eager_fpu field of struct kvm_vcpu_arch
KVM: x86: disable MPX if host did not enable MPX XSAVE features
arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit
arm64: KVM: vgic-v3: Reset LRs at boot time
arm64: KVM: vgic-v3: Do not save an LR known to be empty
arm64: KVM: vgic-v3: Save maintenance interrupt state only if required
arm64: KVM: vgic-v3: Avoid accessing ICH registers
KVM: arm/arm64: vgic-v2: Make GICD_SGIR quicker to hit
KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit
KVM: arm/arm64: vgic-v2: Reset LRs at boot time
KVM: arm/arm64: vgic-v2: Do not save an LR known to be empty
KVM: arm/arm64: vgic-v2: Move GICH_ELRSR saving to its own function
KVM: arm/arm64: vgic-v2: Save maintenance interrupt state only if required
KVM: arm/arm64: vgic-v2: Avoid accessing GICH registers
KVM: s390: allocate only one DMA page per VM
KVM: s390: enable STFLE interpretation only if enabled for the guest
KVM: s390: wake up when the VCPU cpu timer expires
KVM: s390: step the VCPU timer while in enabled wait
KVM: s390: protect VCPU cpu timer with a seqcount
KVM: s390: step VCPU cpu timer during kvm_run ioctl
...
- New drivers for NSA320 and LTC2990
- Added support for ADM1278 to adm1275 driver
- Added support for ncpXXxh103 to ntc_thermistor driver
- Renamed vexpress hwmon implementation
- Minor cleanups and improvements
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW5sANAAoJEMsfJm/On5mBKTEP/2SIXOFN+ew3Lhmz36Z8gDJY
LpVcFjb8S/nRDibvaYjaO5r7p6x2d3jW6wkdpt1V44l5khvODjnaZhH7qZ1xaVuI
qt9xRX0PvHAlwIpXHRNgueNAkAwTuCJqmbbYGrPQJCe4zu0sxiDrpRa117Ym1AJY
NxOts2n/VAjVn0O+F4QiJELDmSpajsVt7QPjUGYfiEHPaGDgPVq+5gqRPeL9hfOu
tjFVWn3YVJTI/Q3N/aB0+XQpwoZdu74RFnr/x7rkjzVcqiNdq0+WtFAIAS9Aw3s1
gZbwRPX7Pu/sNmcVRaj+9rSpzl9uzHbqD4+/+hCuv3LjnyAbLm3NmV2EB1u42SwE
bmqjnCTtC5InlkcKGi85Sv72YcGj5MgddSTQ9TDBKQIW8Z70rnFK/7xPbq776W/L
vFXQ62YZ14lX3sVTMVfntf6BrYeteVbJmP7d9SXeTHfHVSSaxwGrq6kim8m2zi/J
R8YMsVOok0P3ldyua73TIdujYtpz2AZ4vdddDFSlu/m1o/bp642le5HLVuKBpuYy
Szjc26JGL5ymGLAUmeEUt8jOWUqQo9MLw9Gc8kgc/Zui3q+lMJKXZ6dvkgJpnFCL
xw/fB/E6x4pDEhJPe3LeFcKBk/vF6bktEWrrA0rGHrVGJIaOhgPkxyeGV7BdNqFS
DtMy4EcjmlAKOn5oxOL5
=n07O
-----END PGP SIGNATURE-----
Merge tag 'hwmon-for-linus-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
Pull hwmon updates from Guenter Roeck:
- New drivers for NSA320 and LTC2990
- Added support for ADM1278 to adm1275 driver
- Added support for ncpXXxh103 to ntc_thermistor driver
- Renamed vexpress hwmon implementation
- Minor cleanups and improvements
* tag 'hwmon-for-linus-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging:
hwmon: Create an NSA320 hardware monitoring driver
hwmon: Define binding for the nsa320-hwmon driver
hwmon: (adm1275) Add support for ADM1278
hwmon: (ntc_thermistor) Add support for ncpXXxh103
Doc: hwmon: Fix typo "montoring" in hwmon
ARM: dts: vfxxx: Add iio_hwmon node for ADC temperature channel
ARM: dts: Change iio_hwmon nodes to use hypen in node names
hwmon: (iio_hwmon) Allow the driver to accept hypen in device tree node names
hwmon: Add LTC2990 sensor driver
hwmon: (vexpress) rename vexpress hwmon implementation
An almost purely driver related set of changes with no
major changes to the framework, only one patch adding
an unlocked version of the pinctrl_find_gpio_range_from_pin()
library call.
New drivers:
- ST Microelectronics STM32 MCU support: this is a non-MMU
low-end platform for IoT things (etc).
- Microchip PIC32 MCU support: same story as for STM32.
New subdrivers:
- Allwinner SunXi H3 R_PIO controller support.
- Qualcomm IPQ4019 support.
- MediaTek MT2701 and MT7623.
- Allwinner A64
Non-critical fixes:
- gpio_disable_free() for the Vybrid.
- pinctrl single: use a separate lockdep class.
Misc:
- Substantial cleanups and rewrites for the Super-H PFC
driver and subdrivers.
- Various fixes and cleanups, especially Paul Gortmakers
work to make nonmodular drivers nonmodular.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW5rS1AAoJEEEQszewGV1zskIQALNriHdVmPGNIuSZOUk2gqAv
hFNIzFUYM6BK6AL2wD+ZVqQe/EbZtWUF2RqhI2juP8j2WBVMxo8B9ypGjm8qDZ7q
Xtdnd8l22VP0fEmYKTwDgrjSCcMxbXFiPurZBlqCCyb/9raFqLKwx2kcxWqD4PR2
dcC8i/t2JSjGYRRCMcGn+zcKW2zja36xci/ZOExdioHYgFmorCZb9+4NYz+coijv
VEjEy98CG6itBFJ0MS3jHT949TyxpDzWp7hO8LiOAiLR50xCxTlZRT1dObOUQJqk
qhiLK2sTUFJFlTNBUGN0gfMoJo2MpfJIkVre4EV5QNkfy8vjtXeLrbjnSnTXf0r7
5OLMEJPK7mfHd7jsw/nwJMYUoqgeRO9VBXtL2JyGWpsNFBFlJv1YRXaT0AZXkgUq
63BfhTrbtge2xECJ9iqWVdGmmNv2x7lMK6RWqDr72fjONdtmNLDusfNdgYaBWc50
K910IijMX2t2HGQFzuqwQC5HgADPhqBRb2eMcilwwUs5rxzLXX/wer1rhc8guUtK
4DvGZ+wPZd2znQvNAWxsG5azoSfO8J3ibVIkMmaW3NTqyLvnbT9KiNvYuUVg/9NQ
Vcb1d9UnrhAIWzpfpeo4rzr+QIq4j46YHBqreiW/l952Apxpp2lJmV/btK0noPmA
MDTknHc2772QYIBtn01D
=TsdU
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"An almost purely driver related set of changes with no major changes
to the framework, only one patch adding an unlocked version of the
pinctrl_find_gpio_range_from_pin() library call.
New drivers:
- ST Microelectronics STM32 MCU support: this is a non-MMU low-end
platform for IoT things (etc).
- Microchip PIC32 MCU support: same story as for STM32.
New subdrivers:
- Allwinner SunXi H3 R_PIO controller support.
- Qualcomm IPQ4019 support.
- MediaTek MT2701 and MT7623.
- Allwinner A64
Non-critical fixes:
- gpio_disable_free() for the Vybrid.
- pinctrl single: use a separate lockdep class.
Misc:
- Substantial cleanups and rewrites for the Super-H PFC driver and
subdrivers.
- Various fixes and cleanups, especially Paul Gortmakers work to make
nonmodular drivers nonmodular"
* tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
pinctrl: single: Use a separate lockdep class
drivers: pinctrl: add driver for Allwinner A64 SoC
pinctrl: Broadcom Northstar2 pinctrl device tree bindings
pinctrl: amlogic: Make driver independent from two-domain configuration
pinctrl: amlogic: Separate some pin functions for Meson8 / Meson8b
pinctrl: at91: use __maybe_unused to hide pm functions
pinctrl: sh-pfc: core: don't open code of_device_get_match_data()
pinctrl: uniphier: rename CONFIG options and file names
pinctrl: sunxi: make A80 explicitly non-modular
pinctrl: stm32: make explicitly non-modular
pinctrl: sh-pfc: make explicitly non-modular
pinctrl: meson: make explicitly non-modular
pinctrl: pinctrl-mt6397 driver explicitly non-modular
pinctrl: sunxi: does not need module.h
pinctrl: pxa2xx: export symbols
pinctrl: sunxi: Change mux setting on PI irq pins
pinctrl: sunxi: Remove non existing irq's
pinctrl: imx: attach iomuxc device to gpr syscon
pinctrl-bcm2835: Fix cut-and-paste error in "pull" parsing
pinctrl: lpc1850-scu: document nxp,gpio-pin-interrupt
...
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Along with the above mentioned Kconfig changes it seems appropriate
to also rename files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
gcc-6.0 notices that the use of the property_entry in this file that
was recently introduced cannot work right, as we initialize the wrong
field:
raumfeld.c:387:3: error: the address of 'raumfeld_rotary_encoder_steps' will always evaluate as 'true' [-Werror=address]
DEV_PROP_U32, 1, &raumfeld_rotary_encoder_steps, },
^~~~~~~~~~~~
raumfeld.c:389:3: error: the address of 'raumfeld_rotary_encoder_axis' will always evaluate as 'true' [-Werror=address]
DEV_PROP_U32, 1, &raumfeld_rotary_encoder_axis, },
^~~~~~~~~~~~
raumfeld.c:391:3: error: the address of 'raumfeld_rotary_encoder_relative_axis' will always evaluate as 'true' [-Werror=address]
DEV_PROP_U32, 1, &raumfeld_rotary_encoder_relative_axis, },
^~~~~~~~~~~~
The problem appears to stem from relying on an old definition of
'struct property', but it has changed several times since the code
could have last been correct.
This changes the code to use the PROPERTY_ENTRY_INTEGER() macro instead,
which works fine for the current definition and is a safer way of doing
the initialization.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: a9e340dce3 ("Input: rotary_encoder - move away from platform data structure")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJW5j4RAAoJEHm+PkMAQRiGhVEH/0qZbM1J+WnCK92bm9+inCnB
JO2JViGIuCQB5BxljVMil2dzrw85D+dC7+fryr0wVBhhBlr0lXPJGSYCYYTEaI20
Wco5YlTmjRirUwmxWzBXvB5kvTdIaNfNYDcFch6lbsaLUNgqydNKtk08ckO/4k0D
AmaShW8swBiXE/RmHuj8H41ksHsnY8W62dlczEaAIfr4kluPX/kKnyXpmpvmZm1j
sM4fskPlq+Jz5pOXXFsFfrhiBgpSUnwSj1tNwK5+DkmaVnWOkPuwkqLBWqpy4pzm
GTeDBdf5/ixGxgNsZ2VWtbPnc2wEP7SIcu45MU7QFw5kqwDN2nN63BRVXI5Z5qY=
=RFx2
-----END PGP SIGNATURE-----
Merge tag 'v4.5' into next
Merge with Linux 4.5 to get PROPERTY_ENTRY_INTEGER() that is needed to
fix pxa/raumfeld rotary encoder properties.
Pull cpu hotplug updates from Thomas Gleixner:
"This is the first part of the ongoing cpu hotplug rework:
- Initial implementation of the state machine
- Runs all online and prepare down callbacks on the plugged cpu and
not on some random processor
- Replaces busy loop waiting with completions
- Adds tracepoints so the states can be followed"
More detailed commentary on this work from an earlier email:
"What's wrong with the current cpu hotplug infrastructure?
- Asymmetry
The hotplug notifier mechanism is asymmetric versus the bringup and
teardown. This is mostly caused by the notifier mechanism.
- Largely undocumented dependencies
While some notifiers use explicitely defined notifier priorities,
we have quite some notifiers which use numerical priorities to
express dependencies without any documentation why.
- Control processor driven
Most of the bringup/teardown of a cpu is driven by a control
processor. While it is understandable, that preperatory steps,
like idle thread creation, memory allocation for and initialization
of essential facilities needs to be done before a cpu can boot,
there is no reason why everything else must run on a control
processor. Before this patch series, bringup looks like this:
Control CPU Booting CPU
do preparatory steps
kick cpu into life
do low level init
sync with booting cpu sync with control cpu
bring the rest up
- All or nothing approach
There is no way to do partial bringups. That's something which is
really desired because we waste e.g. at boot substantial amount of
time just busy waiting that the cpu comes to life. That's stupid
as we could very well do preparatory steps and the initial IPI for
other cpus and then go back and do the necessary low level
synchronization with the freshly booted cpu.
- Minimal debuggability
Due to the notifier based design, it's impossible to switch between
two stages of the bringup/teardown back and forth in order to test
the correctness. So in many hotplug notifiers the cancel
mechanisms are either not existant or completely untested.
- Notifier [un]registering is tedious
To [un]register notifiers we need to protect against hotplug at
every callsite. There is no mechanism that bringup/teardown
callbacks are issued on the online cpus, so every caller needs to
do it itself. That also includes error rollback.
What's the new design?
The base of the new design is a symmetric state machine, where both
the control processor and the booting/dying cpu execute a well
defined set of states. Each state is symmetric in the end, except
for some well defined exceptions, and the bringup/teardown can be
stopped and reversed at almost all states.
So the bringup of a cpu will look like this in the future:
Control CPU Booting CPU
do preparatory steps
kick cpu into life
do low level init
sync with booting cpu sync with control cpu
bring itself up
The synchronization step does not require the control cpu to wait.
That mechanism can be done asynchronously via a worker or some
other mechanism.
The teardown can be made very similar, so that the dying cpu cleans
up and brings itself down. Cleanups which need to be done after
the cpu is gone, can be scheduled asynchronously as well.
There is a long way to this, as we need to refactor the notion when a
cpu is available. Today we set the cpu online right after it comes
out of the low level bringup, which is not really correct.
The proper mechanism is to set it to available, i.e. cpu local
threads, like softirqd, hotplug thread etc. can be scheduled on that
cpu, and once it finished all booting steps, it's set to online, so
general workloads can be scheduled on it. The reverse happens on
teardown. First thing to do is to forbid scheduling of general
workloads, then teardown all the per cpu resources and finally shut it
off completely.
This patch series implements the basic infrastructure for this at the
core level. This includes the following:
- Basic state machine implementation with well defined states, so
ordering and prioritization can be expressed.
- Interfaces to [un]register state callbacks
This invokes the bringup/teardown callback on all online cpus with
the proper protection in place and [un]installs the callbacks in
the state machine array.
For callbacks which have no particular ordering requirement we have
a dynamic state space, so that drivers don't have to register an
explicit hotplug state.
If a callback fails, the code automatically does a rollback to the
previous state.
- Sysfs interface to drive the state machine to a particular step.
This is only partially functional today. Full functionality and
therefor testability will be achieved once we converted all
existing hotplug notifiers over to the new scheme.
- Run all CPU_ONLINE/DOWN_PREPARE notifiers on the booting/dying
processor:
Control CPU Booting CPU
do preparatory steps
kick cpu into life
do low level init
sync with booting cpu sync with control cpu
wait for boot
bring itself up
Signal completion to control cpu
In a previous step of this work we've done a full tree mechanical
conversion of all hotplug notifiers to the new scheme. The balance
is a net removal of about 4000 lines of code.
This is not included in this series, as we decided to take a
different approach. Instead of mechanically converting everything
over, we will do a proper overhaul of the usage sites one by one so
they nicely fit into the symmetric callback scheme.
I decided to do that after I looked at the ugliness of some of the
converted sites and figured out that their hotplug mechanism is
completely buggered anyway. So there is no point to do a
mechanical conversion first as we need to go through the usage
sites one by one again in order to achieve a full symmetric and
testable behaviour"
* 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
cpu/hotplug: Document states better
cpu/hotplug: Fix smpboot thread ordering
cpu/hotplug: Remove redundant state check
cpu/hotplug: Plug death reporting race
rcu: Make CPU_DYING_IDLE an explicit call
cpu/hotplug: Make wait for dead cpu completion based
cpu/hotplug: Let upcoming cpu bring itself fully up
arch/hotplug: Call into idle with a proper state
cpu/hotplug: Move online calls to hotplugged cpu
cpu/hotplug: Create hotplug threads
cpu/hotplug: Split out the state walk into functions
cpu/hotplug: Unpark smpboot threads from the state machine
cpu/hotplug: Move scheduler cpu_online notifier to hotplug core
cpu/hotplug: Implement setup/removal interface
cpu/hotplug: Make target state writeable
cpu/hotplug: Add sysfs state interface
cpu/hotplug: Hand in target state to _cpu_up/down
cpu/hotplug: Convert the hotplugged cpu work to a state machine
cpu/hotplug: Convert to a state machine for the control processor
cpu/hotplug: Add tracepoints
...
Pull irq updates from Thomas Gleixner:
"The 4.6 pile of irq updates contains:
- Support for IPI irqdomains to support proper integration of IPIs to
and from coprocessors. The first user of this new facility is
MIPS. The relevant MIPS patches come with the core to avoid merge
ordering issues and have been acked by Ralf.
- A new command line option to set the default interrupt affinity
mask at boot time.
- Support for some more new ARM and MIPS interrupt controllers:
tango, alpine-msix and bcm6345-l1
- Two small cleanups for x86/apic which we merged into irq/core to
avoid yet another branch in x86 with two tiny commits.
- The usual set of updates, cleanups in drivers/irqchip. Mostly in
the area of ARM-GIC, arada-37-xp and atmel chips. Nothing
outstanding here"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (56 commits)
irqchip/irq-alpine-msi: Release the correct domain on error
irqchip/mxs: Fix error check of of_io_request_and_map()
irqchip/sunxi-nmi: Fix error check of of_io_request_and_map()
genirq: Export IRQ functions for module use
irqchip/gic/realview: Support more RealView DCC variants
Documentation/bindings: Document the Alpine MSIX driver
irqchip: Add the Alpine MSIX interrupt controller
irqchip/gic-v3: Always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
irqchip/gic-v3-its: Mark its_init() and its children as __init
irqchip/gic-v3: Remove gic_root_node variable from the ITS code
irqchip/gic-v3: ACPI: Add redistributor support via GICC structures
irqchip/gic-v3: Add ACPI support for GICv3/4 initialization
irqchip/gic-v3: Refactor gic_of_init() for GICv3 driver
x86/apic: Deinline _flat_send_IPI_mask, save ~150 bytes
x86/apic: Deinline __default_send_IPI_*, save ~200 bytes
dt-bindings: interrupt-controller: Add SoC-specific compatible string to Marvell ODMI
irqchip/mips-gic: Add new DT property to reserve IPIs
MIPS: Delete smp-gic.c
MIPS: Make smp CMP, CPS and MT use the new generic IPI functions
MIPS: Add generic SMP IPI support
...
* pci/aer:
PCI/AER: Log aer_inject error injections
PCI/AER: Log actual error causes in aer_inject
PCI/AER: Use dev_warn() in aer_inject
PCI/AER: Fix aer_inject error codes
* pci/enumeration:
PCI: Fix broken URL for Dell biosdevname
* pci/kconfig:
PCI: Cleanup pci/pcie/Kconfig whitespace
PCI: Include pci/hotplug Kconfig directly from pci/Kconfig
PCI: Include pci/pcie/Kconfig directly from pci/Kconfig
* pci/misc:
PCI: Add PCI_CLASS_SERIAL_USB_DEVICE definition
PCI: Add QEMU top-level IDs for (sub)vendor & device
unicore32: Remove unused HAVE_ARCH_PCI_SET_DMA_MASK definition
PCI: Consolidate PCI DMA constants and interfaces in linux/pci-dma-compat.h
PCI: Move pci_dma_* helpers to common code
frv/PCI: Remove stray pci_{alloc,free}_consistent() declaration
* pci/virtualization:
PCI: Wait for up to 1000ms after FLR reset
PCI: Support SR-IOV on any function type
* pci/vpd:
PCI: Prevent VPD access for buggy devices
PCI: Sleep rather than busy-wait for VPD access completion
PCI: Fold struct pci_vpd_pci22 into struct pci_vpd
PCI: Rename VPD symbols to remove unnecessary "pci22"
PCI: Remove struct pci_vpd_ops.release function pointer
PCI: Move pci_vpd_release() from header file to pci/access.c
PCI: Move pci_read_vpd() and pci_write_vpd() close to other VPD code
PCI: Determine actual VPD size on first access
PCI: Use bitfield instead of bool for struct pci_vpd_pci22.busy
PCI: Allow access to VPD attributes with size 0
PCI: Update VPD definitions
Pull scheduler updates from Ingo Molnar:
"The main changes in this cycle are:
- Make schedstats a runtime tunable (disabled by default) and
optimize it via static keys.
As most distributions enable CONFIG_SCHEDSTATS=y due to its
instrumentation value, this is a nice performance enhancement.
(Mel Gorman)
- Implement 'simple waitqueues' (swait): these are just pure
waitqueues without any of the more complex features of full-blown
waitqueues (callbacks, wake flags, wake keys, etc.). Simple
waitqueues have less memory overhead and are faster.
Use simple waitqueues in the RCU code (in 4 different places) and
for handling KVM vCPU wakeups.
(Peter Zijlstra, Daniel Wagner, Thomas Gleixner, Paul Gortmaker,
Marcelo Tosatti)
- sched/numa enhancements (Rik van Riel)
- NOHZ performance enhancements (Rik van Riel)
- Various sched/deadline enhancements (Steven Rostedt)
- Various fixes (Peter Zijlstra)
- ... and a number of other fixes, cleanups and smaller enhancements"
* 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (29 commits)
sched/cputime: Fix steal_account_process_tick() to always return jiffies
sched/deadline: Remove dl_new from struct sched_dl_entity
Revert "kbuild: Add option to turn incompatible pointer check into error"
sched/deadline: Remove superfluous call to switched_to_dl()
sched/debug: Fix preempt_disable_ip recording for preempt_disable()
sched, time: Switch VIRT_CPU_ACCOUNTING_GEN to jiffy granularity
time, acct: Drop irq save & restore from __acct_update_integrals()
acct, time: Change indentation in __acct_update_integrals()
sched, time: Remove non-power-of-two divides from __acct_update_integrals()
sched/rt: Kick RT bandwidth timer immediately on start up
sched/debug: Add deadline scheduler bandwidth ratio to /proc/sched_debug
sched/debug: Move sched_domain_sysctl to debug.c
sched/debug: Move the /sys/kernel/debug/sched_features file setup into debug.c
sched/rt: Fix PI handling vs. sched_setscheduler()
sched/core: Remove duplicated sched_group_set_shares() prototype
sched/fair: Consolidate nohz CPU load update code
sched/fair: Avoid using decay_load_missed() with a negative value
sched/deadline: Always calculate end of period on sched_yield()
sched/cgroup: Fix cgroup entity load tracking tear-down
rcu: Use simple wait queues where possible in rcutree
...
Pull read-only kernel memory updates from Ingo Molnar:
"This tree adds two (security related) enhancements to the kernel's
handling of read-only kernel memory:
- extend read-only kernel memory to a new class of formerly writable
kernel data: 'post-init read-only memory' via the __ro_after_init
attribute, and mark the ARM and x86 vDSO as such read-only memory.
This kind of attribute can be used for data that requires a once
per bootup initialization sequence, but is otherwise never modified
after that point.
This feature was based on the work by PaX Team and Brad Spengler.
(by Kees Cook, the ARM vDSO bits by David Brown.)
- make CONFIG_DEBUG_RODATA always enabled on x86 and remove the
Kconfig option. This simplifies the kernel and also signals that
read-only memory is the default model and a first-class citizen.
(Kees Cook)"
* 'mm-readonly-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
ARM/vdso: Mark the vDSO code read-only after init
x86/vdso: Mark the vDSO code read-only after init
lkdtm: Verify that '__ro_after_init' works correctly
arch: Introduce post-init read-only memory
x86/mm: Always enable CONFIG_DEBUG_RODATA and remove the Kconfig option
mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings
asm-generic: Consolidate mark_rodata_ro()
Pull dma_*_writecombine rename from Ingo Molnar:
"Rename dma_*_writecombine() to dma_*_wc()
This is a tree-wide API rename, to move the dma_*() write-combining
APIs closer in name to their usual API families. (The old API names
are kept as compatibility wrappers to not introduce extra breakage.)
The patch was Coccinelle generated"
* 'mm-pat-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
dma, mm/pat: Rename dma_*_writecombine() to dma_*_wc()
Pull ram resource handling changes from Ingo Molnar:
"Core kernel resource handling changes to support NVDIMM error
injection.
This tree introduces a new I/O resource type, IORESOURCE_SYSTEM_RAM,
for System RAM while keeping the current IORESOURCE_MEM type bit set
for all memory-mapped ranges (including System RAM) for backward
compatibility.
With this resource flag it no longer takes a strcmp() loop through the
resource tree to find "System RAM" resources.
The new resource type is then used to extend ACPI/APEI error injection
facility to also support NVDIMM"
* 'core-resources-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
ACPI/EINJ: Allow memory error injection to NVDIMM
resource: Kill walk_iomem_res()
x86/kexec: Remove walk_iomem_res() call with GART type
x86, kexec, nvdimm: Use walk_iomem_res_desc() for iomem search
resource: Add walk_iomem_res_desc()
memremap: Change region_intersects() to take @flags and @desc
arm/samsung: Change s3c_pm_run_res() to use System RAM type
resource: Change walk_system_ram() to use System RAM type
drivers: Initialize resource entry to zero
xen, mm: Set IORESOURCE_SYSTEM_RAM to System RAM
kexec: Set IORESOURCE_SYSTEM_RAM for System RAM
arch: Set IORESOURCE_SYSTEM_RAM flag for System RAM
ia64: Set System RAM type and descriptor
x86/e820: Set System RAM type and descriptor
resource: Add I/O resource descriptor
resource: Handle resource flags properly
resource: Add System RAM resource type
All the drivers support multiple chips, but mv88e6123_61_65 is the
only one that reflects this in its naming. Change it to be consistent
with the other drivers.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on AXP-DB and AXP-GP in same manner - because number of ports
on those boards is the same as number of possible pools, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Armada XP network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-xp.dtsi - for the actual common BM unit (bm@c0000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on:
* A385-DB-AP - each port has its own pool for long and common pool for
short packets,
* A388-ClearFog - same as above,
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
* A388-GP - same as above.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
[gregory.clement@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Armada 38x network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-38x.dtsi - for the actual common BM unit (bm@c8000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch updates csum_ipv6_magic so that it correctly recognizes that
protocol is a unsigned 8 bit value.
This will allow us to better understand what limitations may or may not be
present in how we handle the data. For example there are a number of
places that call htonl on the protocol value. This is likely not necessary
and can be replaced with a multiplication by ntohl(1) which will be
converted to a shift by the compiler.
Signed-off-by: Alexander Duyck <aduyck@mirantis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch updates all instances of csum_tcpudp_magic and
csum_tcpudp_nofold to reflect the types that are usually used as the source
inputs. For example the protocol field is populated based on nexthdr which
is actually an unsigned 8 bit value. The length is usually populated based
on skb->len which is an unsigned integer.
This addresses an issue in which the IPv6 function csum_ipv6_magic was
generating a checksum using the full 32b of skb->len while
csum_tcpudp_magic was only using the lower 16 bits. As a result we could
run into issues when attempting to adjust the checksum as there was no
protocol agnostic way to update it.
With this change the value is still truncated as many architectures use
"(len + proto) << 8", however this truncation only occurs for values
greater than 16776960 in length and as such is unlikely to occur as we stop
the inner headers at ~64K in size.
I did have to make a few minor changes in the arm, mn10300, nios2, and
score versions of the function in order to support these changes as they
were either using things such as an OR to combine the protocol and length,
or were using ntohs to convert the length which would have truncated the
value.
I also updated a few spots in terms of whitespace and type differences for
the addresses. Most of this was just to make sure all of the definitions
were in sync going forward.
Signed-off-by: Alexander Duyck <aduyck@mirantis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.
DT is also used by other projects than Linux kernel. It is not a
good idea to rely on such an unofficial binding.
This commit
- replaces "arm,amba-bus" with "simple-bus"
- drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
one ARCH_EXYNOS.
This depends on clk tree: removal of last presence of ARCH_EXYNOS7.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWz5PsAAoJEME3ZuaGi4PX49cP/jhU8jtgdXvzysVITUPi5Ukv
Rl82rmCrrX//z6n2LpHaqG/bg1ynOeaRa8TLYU/4gQ53fORmk4UgtqNvC54/2+KX
2CNdNko85oX7DIc2nr5RwTNEBspYh0lTvChZtzQqoKVRdMJSiv2Ms5FcnMNYDt5q
xGlQoriTCzlZjt2q6hjlmSZgy8RIn1EeiwsnP3DzmdiX+POgpItfwKln9Ci7E+oz
xGa4N/rdQOA0MeV/wizDyWcaCi8HJSDQfMBq6rvx/NtYSGmJORUggFjmmhfp6wAr
tuVMflDX20ZoDrP5XptbHapoTtOpQny/D7TiFhWvNZc59zpLei1GJOUOhWdq1PVH
om2D59GZ+cNEzDSM/frJiT7VzB32/d479T8DfrwzUahDC2bj+yDPfSK73T72cERs
/eBORjYrjM3h9IEwB4DbE6QrxHondXw3B2PQLq4+40w2sE4efupkiBn6vVKUIT9S
Za2n6l1W1D2XQawz37Ya2/rAybkMaTIURgsRXE/Oe7GKz11pS3oRmYSeDWcOnMsw
PnVL6uTz5zAtoVRygkRVmPv0JUzZgxlNMKfHy7O1zzhSLBtNwXtzGRNyFO+k1yIk
FoWly5/o0mYvW+yU1i5lgBi9Zh5aB5Guq7qsqMoGgDC18u7v+GGAcFhNtwKAXUPy
UDf3Ut2RSTitQnyNyl5m
=XcED
-----END PGP SIGNATURE-----
Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64
Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
one ARCH_EXYNOS.
This depends on clk tree: removal of last presence of ARCH_EXYNOS7.
* tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
clk: samsung: Enable COMPILE_TEST for Samsung clocks
clk: Move vendor's Kconfig into CCF menu section
clk: mediatek: Fix memory leak on clock init fail
clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
clk: xgene: Remove return from void function
clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
Documentation: Update APM X-Gene clock binding for v2 hardware
clk: s2mps11: remove redundant code
clk: s2mps11: remove redundant static variables declaration
clk: s2mps11: allocate only one structure for clock init
clk: s2mps11: merge two for loops in one
clk-divider: make sure read-only dividers do not write to their register
clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
clk: scpi: Fix checking return value of platform_device_register_simple()
clk: mvebu: Mark ioremapped memory as __iomem
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Split out Exynos PMU driver implementation from arm/mach-exynos
to the drivers/soc/samsung which will allow re-use of it on ARM64.
2. Use generic DT cpufreq driver on Exynos542x/5800.
3. Minor cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWz5R8AAoJEME3ZuaGi4PX/dUP/i55BQ3HREph4flgzGZ0mTc2
f9/v5tZ3jkx8uyVCqcHA94faGRPex0q5KfDThQGTf4GpJWvrOSXY7e9ILdz+VNPd
1S1pWluiR+V9TJHRRCz0l7vo81n96EyhHAiCUq0kS9mPbi1aXu0T15kGAWyFa0cK
AF/DAlLrJn7F+0Fspj4Y0YsZLJCt+XxtCxPkGG87aGWPzBBvSgh3PuNHN5sczq3S
l5mQiqulX+Z1KYzN/Qlng2fXmh0llp0qcBdRmQsChhQyYvDCYe3++5efKqyaKXVN
MHAU4sRhgt9CGV6/9J4trJHq/SLqmVQjIoOfZyfvnGIthyIc0hMlT9H5UyWT9cXK
FD5OIWY110XnfUFsViQfEKHeEFjBL6ABSXXITjltDAwc9o2bHKSVtSyq3NLBz4qO
2WzvGSXIhDHtfjBB+wzagrnpOPAwVdVKQ4ZJvuWR7V2aM4Jbrwz9hVCdWKK/iEyU
Oys/SzVzikkvRRolcXsIQphqK6p6tj3H8NY5nDcZZb53x/MxEEk5Pg7oqZNJD5xN
eKsjaSwIgYZ4xaT/mwcLWOc6/XXt7a9SLmQqaYSf4ABWCfZdQtu1an3AzFPUIog+
rJ4IWLJoPkixAPkPZebkyWaIBIktfQjKPWatX+SAm6Y9A9QmC4dgDgoKIYhnTXze
nAUOLxHxx75k9/XQPjFX
=/LNl
-----END PGP SIGNATURE-----
Merge tag 'samsung-soc-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc
Samsung Exynos (and older platforms) improvements for v4.6:
1. Split out Exynos PMU driver implementation from arm/mach-exynos
to the drivers/soc/samsung which will allow re-use of it on ARM64.
2. Use generic DT cpufreq driver on Exynos542x/5800.
3. Minor cleanups.
* tag 'samsung-soc-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: s3c24xx: Avoid warning for inb/outb
ARM: SAMSUNG: Remove unused register offset definition
ARM: EXYNOS: Cleanup header files inclusion
drivers: soc: samsung: Enable COMPILE_TEST
MAINTAINERS: Add maintainers entry for drivers/soc/samsung
drivers: soc: Add support for Exynos PMU driver
ARM: EXYNOS: Split up exynos5420 SoC specific PMU data
ARM: EXYNOS: Split up exynos5250 SoC specific PMU data
ARM: EXYNOS: Split up exynos4 SoC specific PMU data
ARM: EXYNOS: Split up exynos3250 SoC specific PMU data
ARM: EXYNOS: Move pmu specific headers under "linux/soc/samsung"
ARM: EXYNOS: Correct header comment in Kconfig file
ARM: EXYNOS: Use generic cpufreq driver for Exynos5422/5800
ARM: EXYNOS: Use generic cpufreq driver for Exynos5420
ARM: s3c64xx: use "depends on" instead of "if" after prompt
ARM: plat-samsung: use to_platform_device()
ARM: EXYNOS: Code cleanup in map.h
ARM: EXYNOS: Remove unused static mapping of CMU for exynos5
Signed-off-by: Olof Johansson <olof@lixom.net>
The "where" offset was added twice, fix it.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Fixes: 498a92d425 ("ARM: cns3xxx: pci: avoid potential stack overflow")
Signed-off-by: Olof Johansson <olof@lixom.net>
Relaxed the license on the dtsi to permit use in other projects.
Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the Synaptics RMI4 touchscreen to the Ux500 TVK
user interface board. Tested on the U8500 HREFv60plus with
the TVK UIB.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Two more fixes for 4.5:
- One is a fix for OMAP that is urgently needed to avoid DRA7xx chips from
premature aging, by always keeping the Ethernet clock enabled.
- The other solves a I/O memory layout issue on Armada, where SROM and PCI
memory windows were conflicting in some configurations.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW4yITAAoJEIwa5zzehBx38BsQAJRjZOeAec3/F+T8+3pnV0Jl
URcyIFBgXQm6AVW9bwrn7bg9GOcWm0hNk4lgQ/E6KgaZpRVJQ+bhqb79Rz45LhCG
7YmxEXtM8zhVY80/AJsEF0vzogfZsPPI3SiGF9OeIwiMEO91hpRMyvFbOqJC2H40
YX17ARv2BTozLJ2PaW9BKoFAJX2uJJqIB6QOi307m3TVFRPQ5qPpVvh43L1+7flF
ntugOzbEhIg1ZENeb0sNMtrhWlsNlQvulJl2xcp3sbXqkj3sPNIHzyvrPXhxOYQI
VFJKHDC1Op6c2PFK8H0iOQMKq+WWuOidjCGwyg5/PNAoQ4cP+AoD0EpEuXXNjh7e
8DlVhCiYNSJl7M88jahHj1pq3X+CxwQraGANHIa0nijKYp4pqOqv+CZA0sgAX5cq
Ro6U5v5XZxgSR6QGwNBtjCxmXC4z9YaYIP/nkCW2zbPQkaeocKYNykOifp1fOI59
VWufA0OTqk1XjVGcYorpgDaLFUAhgc14JEz1VLQGlw1/M+nVVcfr598FtTWrEoNI
C1L2H7ahqKpVRSYCCtUlXg4TipyurjBk3A91mVBVcrSj/A4ztGkqjwMx995KzP+w
HXI7PSulXK/HDupXslUcUCmVwkI5nxhcH7kuk978zwFFyQvDwB+A1mPysR+Naenz
sI0wqCBHKZj70kyFCflm
=/uWT
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Two more fixes for 4.5:
- One is a fix for OMAP that is urgently needed to avoid DRA7xx chips
from premature aging, by always keeping the Ethernet clock enabled.
- The other solves a I/O memory layout issue on Armada, where SROM
and PCI memory windows were conflicting in some configurations"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory window
ARM: dts: dra7: do not gate cpsw clock due to errata i877
ARM: OMAP2+: hwmod: Introduce ti,no-idle dt property
When the Crypto SRAM mappings were added to the Device Tree files
describing the Armada XP boards in commit c466d997bb ("ARM: mvebu:
define crypto SRAM ranges for all armada-xp boards"), the fact that
those mappings were overlaping with the PCIe memory aperture was
overlooked. Due to this, we currently have for all Armada XP platforms
a situation that looks like this:
Memory mapping on Armada XP boards with internal registers at
0xf1000000:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf8000000 -> 0xffe0000 126M PCIe memory aperture
- 0xf8100000 -> 0xf8110000 64KB Crypto SRAM #0 => OVERLAPS WITH PCIE !
- 0xf8110000 -> 0xf8120000 64KB Crypto SRAM #1 => OVERLAPS WITH PCIE !
- 0xffe00000 -> 0xfff00000 1M PCIe I/O aperture
- 0xfff0000 -> 0xffffffff 1M BootROM
The overlap means that when PCIe devices are added, depending on their
memory window needs, they might or might not be mapped into the
physical address space. Indeed, they will not be mapped if the area
allocated in the PCIe memory aperture by the PCI core overlaps with
one of the Crypto SRAM. Typically, a Intel IGB PCIe NIC that needs 8MB
of PCIe memory will see its PCIe memory window allocated from
0xf80000000 for 8MB, which overlaps with the Crypto SRAM windows. Due
to this, the PCIe window is not created, and any attempt to access the
PCIe window makes the kernel explode:
[ 3.302213] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.307841] pci 0000:00:09.0: enabling device (0140 -> 0143)
[ 3.313539] mvebu_mbus: cannot add window '4:f8', conflicts with another window
[ 3.320870] mvebu-pcie soc:pcie-controller: Could not create MBus window at [mem 0xf8000000-0xf87fffff]: -22
[ 3.330811] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf08c0018
This problem does not occur on Armada 370 boards, because we use the
following memory mapping (for boards that have internal registers at
0xf1000000):
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 => OK !
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Obviously, the solution is to align the location of the Crypto SRAM
mappings of Armada XP to be similar with the ones on Armada 370, i.e
have them between the "internal registers" area and the beginning of
the PCIe aperture.
However, we have a special case with the OpenBlocks AX3-4 platform,
which has a 128 MB NOR flash. Currently, this NOR flash is mapped from
0xf0000000 to 0xf8000000. This is possible because on OpenBlocks
AX3-4, the internal registers are not at 0xf1000000. And this explains
why the Crypto SRAM mappings were not configured at the same place on
Armada XP.
Hence, the solution is two-fold:
(1) Move the NOR flash mapping on Armada XP OpenBlocks AX3-4 from
0xe8000000 to 0xf0000000. This frees the 0xf0000000 ->
0xf80000000 space.
(2) Move the Crypto SRAM mappings on Armada XP to be similar to
Armada 370 (except of course that Armada XP has two Crypto SRAM
and not one).
After this patch, the memory mapping on Armada XP boards with
registers at 0xf1 is:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
And the memory mapping for the special case of the OpenBlocks AX3-4
(internal registers at 0xd0000000, NOR of 128 MB):
- 0x00000000 -> 0xc0000000 3G RAM
- 0xd0000000 -> 0xd1000000 1M internal registers
- 0xe800000 -> 0xf0000000 128M NOR flash
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Fixes: c466d997bb ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards")
Reported-by: Phil Sutter <phil@nwl.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Force the DRA7xx Ethernet internal clock source to stay enabled
per TI erratum i877:
http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Otherwise, if the Ethernet internal clock source is disabled, the
chip will age prematurely, and the RGMII I/O timing will soon
fail to meet the delay time and skew specifications for 1000Mbps
Ethernet.
This fix should go in as soon as possible.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/omap-critical-fixes-for-v4.5-rc/20160307014209/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW3UuoAAoJEMePsQ0LvSpL4JIP/j9A1ax1c6kGfNujSzBMrVL3
I68l27ohfbo/MKMc/KsqkdahzGimIUmqkJGxrnA19UMhfyMb6l3pzlVswxfUUd10
EXl/aKlPDa+Xl+A+TCwK78C69ZXHk4nqsNDSixuoIVfxM2uTZZZmNK3FOR+/EaQ8
kUq3zwkg31HgsYxIyvqcCwpsxmDwKXx6fQ3sX5A6tQGvtsdeNofWJOVoGpZe0Ott
tmt09VEvSGvXVEL1Um6U5A+8Mw6GPWa9/wih8nYaE70BswuOmIMUxeCkrShDadpn
4Z8rqZg1Q8sdnI7ZCARS2WZ63+wrcjq04Yycf7m8feUc7cIDqlahWnrIWKuvpPAz
P20LgrwRQDgifM2TzJupPRUKX+7BoACOXTIt2A3HuOIsZRfqysFx4qoOEdQNBlVq
mOOwA/o8ly8hJI7uym8elrPY4MjZ4f6l2h/mFom0XrlS/1NcxXwuGqi9SJNneFSm
ALyCIW7YnemoOex0tUcHUg2fiGaRceWlSmzHxI0WgVyOj86hrXc8OnpjnPmuhMQV
i4pkL4Y1/UxZepd0b6QOTUC+LQvsWL008XLUr0SPm1d2Co9sxyzN8i0pXh07bsm0
sOflS6DtwWSNenX/OVVQWk0r5amNwiFFpiw7tBWIeXYi4glhyizqdGjbzxRjxJUf
QfFex23RAWtf/1ZrvqQO
=kJw8
-----END PGP SIGNATURE-----
Merge tag 'for-v4.5-rc/omap-critical-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
ARM: OMAP2+: critical DRA7xx fix for v4.5-rc
Force the DRA7xx Ethernet internal clock source to stay enabled
per TI erratum i877:
http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Otherwise, if the Ethernet internal clock source is disabled, the
chip will age prematurely, and the RGMII I/O timing will soon
fail to meet the delay time and skew specifications for 1000Mbps
Ethernet.
This fix should go in as soon as possible.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/omap-critical-fixes-for-v4.5-rc/20160307014209/
* tag 'for-v4.5-rc/omap-critical-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending:
ARM: dts: dra7: do not gate cpsw clock due to errata i877
ARM: OMAP2+: hwmod: Introduce ti,no-idle dt property
Signed-off-by: Olof Johansson <olof@lixom.net>
Rename dma_*_writecombine() to dma_*_wc(), so that the naming
is coherent across the various write-combining APIs. Keep the
old names for compatibility for a while, these can be removed
at a later time. A guard is left to enable backporting of the
rename, and later remove of the old mapping defines seemlessly.
Build tested successfully with allmodconfig.
The following Coccinelle SmPL patch was used for this simple
transformation:
@ rename_dma_alloc_writecombine @
expression dev, size, dma_addr, gfp;
@@
-dma_alloc_writecombine(dev, size, dma_addr, gfp)
+dma_alloc_wc(dev, size, dma_addr, gfp)
@ rename_dma_free_writecombine @
expression dev, size, cpu_addr, dma_addr;
@@
-dma_free_writecombine(dev, size, cpu_addr, dma_addr)
+dma_free_wc(dev, size, cpu_addr, dma_addr)
@ rename_dma_mmap_writecombine @
expression dev, vma, cpu_addr, dma_addr, size;
@@
-dma_mmap_writecombine(dev, vma, cpu_addr, dma_addr, size)
+dma_mmap_wc(dev, vma, cpu_addr, dma_addr, size)
We also keep the old names as compatibility helpers, and
guard against their definition to make backporting easier.
Generated-by: Coccinelle SmPL
Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: airlied@linux.ie
Cc: akpm@linux-foundation.org
Cc: benh@kernel.crashing.org
Cc: bhelgaas@google.com
Cc: bp@suse.de
Cc: dan.j.williams@intel.com
Cc: daniel.vetter@ffwll.ch
Cc: dhowells@redhat.com
Cc: julia.lawall@lip6.fr
Cc: konrad.wilk@oracle.com
Cc: linux-fbdev@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: luto@amacapital.net
Cc: mst@redhat.com
Cc: tomi.valkeinen@ti.com
Cc: toshi.kani@hp.com
Cc: vinod.koul@intel.com
Cc: xen-devel@lists.xensource.com
Link: http://lkml.kernel.org/r/1453516462-4844-1-git-send-email-mcgrof@do-not-panic.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Include pci/pcie/Kconfig directly from pci/Kconfig, so arches don't
have to source both pci/Kconfig and pci/pcie/Kconfig.
Note that this effectively adds pci/pcie/Kconfig to the following
arches, because they already sourced drivers/pci/Kconfig but they
previously did not source drivers/pci/pcie/Kconfig:
alpha
avr32
blackfin
frv
m32r
m68k
microblaze
mn10300
parisc
sparc
unicore32
xtensa
[bhelgaas: changelog, source pci/pcie/Kconfig at top of pci/Kconfig, whitespace]
Signed-off-by: Sasa Bogicevic <brutallesale@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Several cases of overlapping changes, as well as one instance
(vxlan) of a bug fix in 'net' overlapping with code movement
in 'net-next'.
Signed-off-by: David S. Miller <davem@davemloft.net>
For a long time all architectures implement the pci_dma_* functions using
the generic DMA API, and they all use the same header to do so.
Move this header, pci-dma-compat.h, to include/linux and include it from
the generic pci.h instead of having each arch duplicate this include.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Errata id: i877
Description:
------------
The RGMII 1000 Mbps Transmit timing is based on the output clock
(rgmiin_txc) being driven relative to the rising edge of an internal
clock and the output control/data (rgmiin_txctl/txd) being driven relative
to the falling edge of an internal clock source. If the internal clock
source is allowed to be static low (i.e., disabled) for an extended period
of time then when the clock is actually enabled the timing delta between
the rising edge and falling edge can change over the lifetime of the
device. This can result in the device switching characteristics degrading
over time, and eventually failing to meet the Data Manual Delay Time/Skew
specs.
To maintain RGMII 1000 Mbps IO Timings, SW should minimize the
duration that the Ethernet internal clock source is disabled. Note that
the device reset state for the Ethernet clock is "disabled".
Other RGMII modes (10 Mbps, 100Mbps) are not affected
Workaround:
-----------
If the SoC Ethernet interface(s) are used in RGMII mode at 1000 Mbps,
SW should minimize the time the Ethernet internal clock source is disabled
to a maximum of 200 hours in a device life cycle. This is done by enabling
the clock as early as possible in IPL (QNX) or SPL/u-boot (Linux/Android)
by setting the register CM_GMAC_CLKSTCTRL[1:0]CLKTRCTRL = 0x2:SW_WKUP.
So, do not allow to gate the cpsw clocks using ti,no-idle property in
cpsw node assuming 1000 Mbps is being used all the time. If someone does
not need 1000 Mbps and wants to gate clocks to cpsw, this property needs
to be deleted in their respective board files.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Introduce a dt property, ti,no-idle, that prevents an IP to idle at any
point. This is to handle Errata i877, which tells that GMAC clocks
cannot be disabled.
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tiny fixes branch this week, in fact only one patch.
Turns out the USB support for a Renesas board was developed on a pre-release
board that ended up being changed before shipping. To avoid breakage on those
boards, and avoid confusion, it's a reasonable idea to patch now instead of
later. There are no known users of the pre-release variant any more.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW3ImHAAoJEIwa5zzehBx3/tcP/2lW14P7exYAcqIke9qagz9D
88n59MDwu+GOaiU3G/SbzClDItmEKs/sTZjPvl9l/n1cFEj//9smrsK7brklE8wk
IB3cIUBzJCSXNffBPLs0qXjrIgf86c/t5LNJCsXXritY83/wT6+YgIUKv3IaGjqW
mxXvf3Y7ymqVB7favDoThSeT8/fApRBp8d0+Z3Dr31CvmmMTp4nRg2773E2ZZYCj
pC7LaPZvAUN7ko5pnl6FtY19H+bj6hsvk2dV68xotQAvQZudDbhgZUb+yZhWxOiF
BXNYNRQxh8nVhILG8Iup48I5NEJbMmFKR0PwGaIaI29Mo2eR6FX1NXD3e6iGFx2+
xS7Jr4AW7+7t4zzOsmTUGkDJkxjkMq9wO7xkrqotYE0lPqyOKqswaOHQYKDNXJK6
ejGuzIpSvKWuuiUQSYkbm6+nR4tob96SU6fz25/ZZxRNqrd9+XCqpgKu/ZFSusYM
84C/5mwt5KzAeXoB5GnuEUIfm5uRGWWOxPYa4CknPVsEQTS0bBEiAjyYm+grPctB
DvXq4K8Ba5AJ2pA1qe8cQ0bhJuTyqkQwv9nQN5bO5SUgrAI/8ha/bSoI+AJWXmGE
RZ1Lw3JeLuaUWSPZdcCp1gQh6zWdS6bbZIPxJgZd6wMkBAdRrJscvVXwSS4lWJW5
rDINOiN37GE7/iKISuvs
=aA8l
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fix from Olof Johansson:
"Tiny fixes branch this week, in fact only one patch.
Turns out the USB support for a Renesas board was developed on a
pre-release board that ended up being changed before shipping. To
avoid breakage on those boards, and avoid confusion, it's a reasonable
idea to patch now instead of later. There are no known users of the
pre-release variant any more"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: porter: remove enable prop from HS-USB device node
Pull ARM fixes from Russell King:
"Just two ARM fixes this time: one to fix the hyp-stub for older ARM
CPUs, and another to fix the set_memory_xx() permission functions to
deal with zero sizes correctly"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8544/1: set_memory_xx fixes
ARM: 8534/1: virt: fix hyp-stub build for pre-ARMv7 CPUs
Add iio-hwmon node to expose the temperature channel on Vybrid as
hardware monitor device using the iio_hwmon driver.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Change iio_hwmon nodes to use hypen in node names instead of
underscore.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Given a device which uses arm_coherent_dma_ops and on which
dev_get_cma_area(dev) returns non-NULL, the following usage of the DMA
API with gfp=0 results in memory corruption and a memory leak.
p = dma_alloc_coherent(dev, sz, &dma, 0);
if (p)
dma_free_coherent(dev, sz, p, dma);
The memory leak is because the alloc allocates using
__alloc_simple_buffer() but the free attempts
dma_release_from_contiguous() which does not do free anything since the
page is not in the CMA area.
The memory corruption is because the free calls __dma_remap() on a page
which is backed by only first level page tables. The
apply_to_page_range() + __dma_update_pte() loop ends up interpreting the
section mapping as an addresses to a second level page table and writing
the new PTE to memory which is not used by page tables.
We don't have access to the GFP flags used for allocation in the free
function. Fix this by adding allocator backends and using this
information in the free function so that we always use the correct
release routine.
Fixes: 21caf3a7 ("ARM: 8398/1: arm DMA: Fix allocation from CMA for coherent DMA")
Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Keep a list of allocated DMA buffers so that we can store metadata in
alloc() which we later need in free().
Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow zero size updates. This makes set_memory_xx() consistent with x86, s390 and arm64 and makes apply_to_page_range() not to BUG() when loading modules.
Signed-off-by: Mika Penttilä mika.penttila@nextfour.com
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ixp4xx and pxa25x both use this driver and provide a slightly
different set of register definitions for it. Aside from that,
the definition in the ixp4xx-regs.h header conflicts with the
on in the pxa27x device driver when compile-testing that:
In file included from ../drivers/usb/gadget/udc/pxa27x_udc.c:37:0:
../drivers/usb/gadget/udc/pxa27x_udc.h:26:0: warning: "UDCCR" redefined
#define UDCCR 0x0000 /* UDC Control Register */
^
In file included from ../arch/arm/mach-ixp4xx/include/mach/hardware.h:27:0,
from ../arch/arm/mach-ixp4xx/include/mach/io.h:18,
from ../arch/arm/include/asm/io.h:194,
from ../include/linux/io.h:25,
from ../include/linux/irq.h:24,
from ../drivers/usb/gadget/udc/pxa27x_udc.c:23:
../arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h:415:0: note: this is the location of the previous definition
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
This addresses both issues by moving all the definitions into the
pxa25x_udc driver itself. It turns out the only difference between
them was 'UDCCS_IO_ROF', and that could well be a mistake when it
was incorrectly copied from pxa25x to ixp4xx.
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Drop support for platform data passed via a C-structure and switch to
device properties instead, which should make the driver compatible with all
platforms: OF, ACPI and static boards. Static boards should use property
sets to communicate device parameters to the driver.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
-----------
- Add a new stm32f469 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rYKAAoJEMo4jShGhw+J6AAP/jho9aHsFYzHCMChp4fP8wiI
w9gLsD0m4Nz5VI16TInSwBTI0/PqiEEQ/MYWVJ/yMMo9De00Wnm48bAtEZ0UHMIP
ycwBrasdakpbtcuptEFjr8TIKIpnwK1wTgg2NFfMvYIs93LPOe/R3bjPg8qCCVoM
1YID1Kf27IHH1sgfqDBy7ZAoElW9z9EQwEaMwxEn7pABXv4Aq8SHZWbU6rW07pnj
h6x6wQL23tK9Afq+KGHi8l+kBHElF2xDQZPCFIKkS1u+y9dqptvdNxezGXxWswDy
R5ixRfype4NDKCibxmsIfPlc2eExoOOvyxqNTwdttUSeP6QdOMBFKQuxeY3nonqv
f0ZXGYz246iSRtN+gwjN69QYC/CtwNdlhn8MwQvvxavDHdx2ALZUC9jIZYJD+5LO
DMwUvya0FmOabs2CfavaS+NXGRwVzjvhyLtWr7Z48BYx3tWRYvYoavkK35U2Fvk/
wJ8IBm5yTT9WWhV3lIa8l7+CGwWi0x5yMZI+BWIZb54AFrdR8IJ52RQJ/exMRrn4
vCF1n7O2gtQSBv65ImFzaB9g1XrwN25G7em3bUc2KIbeCpQ+1kpZSa7pkDMsKZGX
nJ1auB9ght1D8uGxJ2hqjGwwhqE7RtT7tln8hOtykE3qBPNAytUhyAV4t4mFJ1zb
1bcNLvDGfm3chFREEVr6
=bK+a
-----END PGP SIGNATURE-----
Merge tag 'stm32-soc-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/soc
Merge "STM32 SoC updates for v4.6 #2" from Maxime Coquelin:
Highlights:
-----------
- Add a new stm32f469 SoC
* tag 'stm32-soc-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: stm32: Identify a new SoC - STM32F469
- Enable runtime revision detection for dra7 to avoid multiple dts
files for various variants
- Add dma_slave_map for omap1/2/3 legacy mode booting
- Add RTC interconnect target data for ti81xx and am43x
- Add custom reset handler for PCIeSS
- Add eDMA interconnect target data for dra7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hq3AAoJEBvUPslcq6Vz/H8QAMHYtBHdsUgNeH8mD0s65K70
7sWyaolm9p9xCjhFMmpgesOwEzkFzJBOXZ2edKa8wt0depk06AOJLZZLvNNYJoFB
AxF0+vRQmy2W+83hDSjnIsntxP4iN6w24jKDMOfXIsiwbFa2tX25xbAvcuCP3V8N
pWyNvSJUZcr1ZoOxRNulCp4+NgkzN90QPrvCKRITMb1mx/HAclVmaaHL+jczNmCE
3YM40+25yuzWqDe3jsvA3vPq/ZZTQmUxSF/gDSPCnNYdnWtVqd0DzRc1lYp5MHJL
e1teA/8wLHKvX+cVgyZSt9lb7RwymdWZreodzhI4rzKuFQvq5ySUQCJpGXD2YFg2
4W49CpqaDcZJjpih/TjXpyz66paArKBheg31NskTfALKEFxUPM8FXRbClmQyOvp+
wJ5ZtJbdYoxMJbqISDyIx8OgA2MkimGhPieTFzCCBelqrD9ovX51Ggy2ta0hSLx5
hZuyUw6oWMRCMQ1uZxuug34tnI2h5kyx2kM9gUBsmrO2/bKD4FfkHr9WJQ8EWavy
+r1NX5IlKoLhtThTzLqfyzqQMRgFq+FDo9Hy8NCXKgMWoURe/lZCtOCDivsf3VrI
eQ1HzJVRCBl1soA5RAow3b0o73nftXRPC78tcsxcAy9eQWLuxTVX0TxhfX1Cc7nO
sKjq/8q7tyjvxc0YHuOc
=tJb7
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap soc changes for v4.6 merge window" from Tony Lindgren:
SoC related changes for omaps for v4.6 merge window:
- Enable runtime revision detection for dra7 to avoid multiple dts
files for various variants
- Add dma_slave_map for omap1/2/3 legacy mode booting
- Add RTC interconnect target data for ti81xx and am43x
- Add custom reset handler for PCIeSS
- Add eDMA interconnect target data for dra7
* tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
ARM: OMAP2+: Add rtc hwmod configuration for ti81xx
ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
ARM: OMAP2+: DMA: Provide dma_slave_map to omap-dma for legacy boot
ARM: OMAP1: DMA: Provide dma_slave_map to omap-dma
ARM: OMAP: DRA7: Make use of omap_revision information for soc_is* calls
ARM: AM43XX: hwmod: Add rtc hwmod
ARM: DRA7: hwmod: Add reset data for PCIe
ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJW1Z/XAAoJEFBXWFqHsHzOfUEH/1oiBDMBJEKH8/vmipV5cPmw
TAcK4W/1mS0SZo8xSYyi0iGcs5loA7fiypBZv6tKxI2IZS1w3sbJ0eHeeUUkURsG
okMpHCMeuEdjnWH/nTdABKGIlK1nAtwuDuD0BJqlk1VDLY/pIUY5kkoWsrXMlzwO
VkS2ic90HjsijmLH5y38kgo6RvkDDBxMzl8lzTxwfMNO8P5zCn9Wiqeerlbt/+Nw
+n8aDzow4XKuOaHaoh6/C9RSKkobCAs/RVwoYUhv4QCk1zC6rJ1Oq6yuYGJgiIOX
+gtdAIxTVv4RDJfEWEMT+N9SFM4qcFDAGtGPoXZyRKeedC5/xXuD2yNn2RUzShc=
=RoB/
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "i.MX SoC update for 4.6" from Shawn Guo:
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Make reset_control_ops const
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
ARM: imx: select ARM_CPU_SUSPEND only for imx6
ARM: mx25: Add basic suspend/resume support
ARM: imx: Add msl code support for imx6qp
ARM: imx: enable big endian mode
ARM: imx: use endian-safe readl/readw/writel/writew
ARM: imx7d: correct chip version information
ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
ARM: imx6: fix cleanup path in imx6q_suspend_init()
for the v4.5-rc cycle:
- Add back optimized cpuidle parameters for 34xx that were
incorrecly removed earlier with cpuidle cleanup
- Fix SSI for omap36xx to get modem working on N950/N9
- A series of omap hwmod fixes via Paul Walmsley <paul@pwsan.com>
to fix SSI for omap36xx for modem on N950/N9, fix for
OCP2SCP sysconfig idle mode, and reset data for PCIe on
dra7
- Fix out of range register access for omap3 control module
if syscon max_register is initialized like v4.6 will be
doing
- Fix l4_ls interconnect clocks for 81xx, it should always
be sysclk6_ck
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hi8AAoJEBvUPslcq6Vz2DQP/jGerFh+98FhppQdCiu/xgY7
y+GB97UF8I6y4zoQ2NT4/hm7/RJDtZKLtyZkWQYvZFYfMbKsPyyITF9WSN5m4eIy
Z9F1PMl19AgY4F3K5E0aJ/kTd9hEMEDTMnwSfQy/kToCEJQLX8QZZx49pmV13qgx
vL81Unj7lWb0cWspRN8ShKNK49oFfwzGc+EFudx0aIoIckGEHjBAgJ7WDEN6jdhC
EnQbEhUajC5deCWvP1+SjopMt5tF5kJOSRfhHOfsyGvonOdrXAXZ1IgLKla+T2Zw
twOBmdHzou1LuJo0m5nr6R6cEegtqV+Hi2wLYvQ+Fach6xBUzUAB8xvWvKrGF2Eo
8xmRuPaUWU7raxdHbmsh/VF8dpUw9M+k/X2FMA3axPk6Z1mt9XlJpCTCvJMzg09C
M+yuuPjYRB+Eh/VXjoL33n6LSMYmgKVRy6wyYBPJgtec0uG5HRaP07UiappojrRf
+7kWyxSyhOcUzUa04sbo4IqgRU3vIpucB3z3WsRzGL/d8RoW2Ox2/49WmSKvO4NA
BxRpu2mTT6o8CIoaqaKrhPWjkXFjiWujqzgt/Li9qzzIlsUzJuAnJpeKBgLlBwIy
HrzdYT4+Et1ofbIcaQ7uhQ/Wq+Aw8anJbn2X9M5FDOTLlUs0s0JO5ZC6v8hj271+
hpS6cFLs/bB8cvBELpQd
=pwoK
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "omap non-urgent fixes for v4.6 merge window" from Tony Lindgren:
Fixes for omaps for v4.6 merge window that are not urgent
for the v4.5-rc cycle:
- Add back optimized cpuidle parameters for 34xx that were
incorrecly removed earlier with cpuidle cleanup
- Fix SSI for omap36xx to get modem working on N950/N9
- A series of omap hwmod fixes via Paul Walmsley <paul@pwsan.com>
to fix SSI for omap36xx for modem on N950/N9, fix for
OCP2SCP sysconfig idle mode, and reset data for PCIe on
dra7
- Fix out of range register access for omap3 control module
if syscon max_register is initialized like v4.6 will be
doing
- Fix l4_ls interconnect clocks for 81xx, it should always
be sysclk6_ck
* tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix hwmod clock for l4_ls
ARM: OMAP2+: Fix out of range register access with syscon_config.max_register
ARM: OMAP3: Add cpuidle parameters table for omap3430
ARM: DRA7: hwmod: Add reset data for PCIe
ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
-----------
- Enable GPIO led driver in stm32_defconfig
- Introduce a config fragment to override RAM base address
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rV2AAoJEMo4jShGhw+JXIgP/iTq3X5thCRCnhj9gyVlaZAC
Iv+HE+ZaFmpwDnzHfmtrDVnKhHMc3SFqNcCuD+FFLdfZoqB+Qi/RfK+DHqbFIfwY
COa41koW1pRgjqHTzPmJqVxB2wiETvWOE6KUjZrfT3EUGdvghiy9EAnyN0RppbIp
CNivabvnqKEiVk9rqtbx6veWBw0aQyg2oL0d8ypPsGP8u87FmIqWpDK0vw8c2JyV
MuCEt/sDBMtWNr89ylJqAIUiRlm/pFhQY32BxlkfYfqjz1xBac/5BihhK1cP2cZW
FtDV4Y3IF4Lm+c41EXazYbiduY7OMkKb5XVUGsjFfZKNxTTQbzOvahgpW7cImFPE
kMzdV8mVD0g0eQumXNeg2wSJgfjxx6kxGWwxUVaFAL82FizuRyDLruDnBmfkQ92P
uVnFH6wIs9oiBNmVaBibMun61aexLVjzJqPepI+Ray9tJInwz5QsK+oRUe8hXyAJ
QmExU49z/dY49NYGIyTqE0wQx26gjmyYUqFnUEktsXMkKzuwU99SxUwxhUhgr48H
agr1fpj4g1gBHQdoHPPvCfb1Jp60Hnl0iSmr5Yv5ay5n1xs+r2IOzenZaY0UaTiy
alJLf7yHSyNwmPgxgpO0+Z/Yc3faQgTu5q1FatDxTmD3rDjDd0JMhv75O9+Z/k6e
AGBkwtGMi1040O3LpvMI
=dBNt
-----END PGP SIGNATURE-----
Merge tag 'stm32-defconfig-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/defconfig
Merge "STM32 defconfig updates for v4.6 #1" from Maxime Coquelin:
Highlights:
-----------
- Enable GPIO led driver in stm32_defconfig
- Introduce a config fragment to override RAM base address
* tag 'stm32-defconfig-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: configs: Add new config fragment to change RAM start point
ARM: config: Enable GPIO Led driver in stm32_defconfig
for v4.6 merge window:
- Enable IOMMU and omap3isp so we can enable TVP5150/1 video
decoder
- Enable at24 eeprom for revision detection on beagle-x15
- Enable LP872x regulator for both omap2plus_defconfig and
multi_v7_defconfig as it's needed at least by LG Optimus
Black
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1hwfAAoJEBvUPslcq6Vz9UwQAKKtMT4EsO+oBFYNtwippBF0
o2RhThB0Pwve48H+sQOvdeDz0FAisAYd9kecG033QMLEYrASneXaM0AYkeDIjJCE
5SzwLtNumwhhYbeoQNCIcC+V/rDAplD4KR1WSteeWBPwHweGK3cWfczWN8FRmNqk
iPfDqSb70C8bUpQeHhGc2xRGthVDKpZeeO9gsfAYOBJGHkMfe2bjyaGRUynoN/Az
UyBOmr2gmw+YQTknYtsdHnxXBLlhUz6bDKsoB0wXtP4BSrAeenf+Tm7jmWiDZbeG
wSNmnp7DM/l5kBb8M8BJRfNDpk44ro+OkUYXGUoBmP0Mw3OFeqhXBlj3gugtQR7j
xQ9BJ4wcWwvxP1rukeqTpwobsMydenJCrw57I7iW+bLn5D6YMx/TJIITeq895tcg
6xCGlY++78W20NkGtctQMtqpt9zV/HTxQRkJIPzfSd3b9mfWTLimK+DYKwGxgym+
LgoCQwPJrZAZzvE3/nkyhx0kTEPbyRbCvT33xBRerPIYgGRq+DSZFmsLyFW1OKdT
VT1uOHuChqertqTUONdW6d6QQuwo6PheOmFz7Z3fJbizu5Uuim+YgkxxKBL+5kKg
VKJuEfAs2CqS506yCxtGG/eTrmxWHXkSXu75H1yXPVcnn38vjwH9wqiorcKOO9Em
FNN5I14TW4Lt+DqkNpx8
=JVC1
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig
Merge "omap defconfig changes for v4.6 merge window" from Tony Lindgren:
Defconfig changes for omap2plus_defconfig and multi_v7_defconfig
for v4.6 merge window:
- Enable IOMMU and omap3isp so we can enable TVP5150/1 video
decoder
- Enable at24 eeprom for revision detection on beagle-x15
- Enable LP872x regulator for both omap2plus_defconfig and
multi_v7_defconfig as it's needed at least by LG Optimus
Black
* tag 'omap-for-v4.6/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: multi_v7_defconfig: Enable LP872x regulator support
ARM: omap2plus_defconfig: Enable LP872x regulator support
ARM: omap2plus_defconfig: Enable AT24 eeprom
ARM: omap2plus_defconfig: Enable TI TVP5150 video decoder support
ARM: omap2plus_defconfig: Enable ISP support and dependencies
ARM: omap2plus_defconfig: Enable OMAP IOMMU support
1. We want thermal for Exynos7 TMU unit to monitor the temperature.
2. Enable the drivers for PMIC used on Exynos7-based Espresso board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1VxBAAoJEME3ZuaGi4PXz/wP/1/mAzScizlcdGi7k1DmP7fZ
9rsAiXYjIjxcI96L0qrEBCZFDdSwBv/pCRTuCg94FClFYBuW+IZmkTeWPHvtsB5O
my4Xk3O5WEQbpFPUTZwl8yTlRSwlRdob7lGBFWuapqiCcws6l5xRffG1n6itqN32
RTzLfeSAAj9zg94EX8UaNYcW9T0aIR/QGOIRXfziorACj5FdSiNvnXNwZBPj39ti
X47h3BuLjCio0LPPSwNf4Z7XqenOX8z77Y8WTOi0WaRcnirdyjlOFTCLMCYvWIVw
oih2xofdkDH+QsPOY1Qj96C6I1cUhqC3Z+fvz0PiPfk4Lit7hts+tdZ/8HBdX4V2
tLodKxL7QowlrwbcRWn7i/MujiOTv6H0+OlJWucrOSFwmYqce8kNdyI/DIp5wNyS
5NpfLX47SzL8sF4KnxdS8dvYrIT+mJUfuNAexNE44orwrm9AHbmTMNs1ZrGJd4Y7
wlHg/q0m2lwhG8hvVUiDUwTwkljP1Z94zjJSGK0JMIlBwVbCEKNmBEJZv54RseMV
47xDisM6RY1SWWx497vXaPcP42AivQn9a/rPJoaeEIsxJgQDTeHmbiCSWJYe43QD
blKjwBb35QORnkc6tkBDOREFahF0uWVYS+7NOHcbDih2efb65rHAURzrnJIUBXTZ
QR9mA4PxcR54BFs9RznS
=T9z9
-----END PGP SIGNATURE-----
Merge tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64
Merge "ARM64 defconfig changes for Exynos based boards for v4.6" from Krzysztof Kozlowski:
1. We want thermal for Exynos7 TMU unit to monitor the temperature.
2. Enable the drivers for PMIC used on Exynos7-based Espresso board.
* tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: Enable Samsung MFD and related configs
arm64: defconfig: Enable exynos thermal config
ARM: multi_v7_defconfig: Remove MAX77802 RTC Kconfig symbol
ARM: exynos_defconfig: Remove MAX77802 RTC Kconfig symbol
rtc: max77686: Cleanup and reduce dmesg output
rtc: Remove Maxim 77802 driver
rtc: max77686: Properly handle regmap_irq_get_virq() error code
rtc: max77686: Fix unsupported year message
rtc: max77686: Add max77802 support
rtc: max77686: Add an indirection level to access RTC registers
rtc: max77686: Use a driver data struct instead hard-coded values
rtc: max77686: Use usleep_range() instead of msleep()
rtc: max77686: Use ARRAY_SIZE() instead of current array length
rtc: max77686: Fix max77686_rtc_read_alarm() return value
ARM: exynos_defconfig: Enable s5p-secss driver
ARM: exynos_defconfig: Enable NEON, accelerated crypto and cpufreq stats
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- addition of the NAND flash node
- addition of the dma properties for UART/USART nodes
- one update of the sama5d2 Xplained phy node
- addition of USB pinmux, button and leds
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJW1w1UAAoJEAf03oE53VmQmkAIALy7FfwfsXwV4EBMjrkyBbHF
6fODom/DihCOaATD1tOaKaW0imyNXRu6qsnV5PZNRU7SCbJffolcY852iAW8I6hL
qmdTumHGQszMJu95Nz+au04l9rqGvzeQ3v136YueMFtn6oQydF/6ttQzjjcCRKPy
0FRTk6IKroKZ2qRl4dbvnMF1QJW+3eSe5U3mULEkTdc2Fup60cfwP9Z8uzzYIYgf
CnMwyakQxqp/Y9tYTIMS/RKj+VuQxI0+nN6f8dWKsWbIKIEk6n8W+RtrKdYl1GZ2
VT0GsCJ/qw+EHqk3dD45tFFIvdiXIc9UElB4p+s7CLqX4GAShN1JNkidkBrTgKw=
=7QLe
-----END PGP SIGNATURE-----
Merge tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/dt
Merge "at91: dt for 4.6 #2" from Nicolas Ferre:
Second 4.6 DT series, all patches for sama5d2 and its Xplained board:
- addition of the NAND flash node
- addition of the dma properties for UART/USART nodes
- one update of the sama5d2 Xplained phy node
- addition of USB pinmux, button and leds
* tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
-----------
- Fix clock references in GPIO nodes
- Add early support to stm32f469 MCU
- Add USB HS support in host mdoe to stm32429-eval board
- Add Ethernet support to stm32429-eval board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1rPwAAoJEMo4jShGhw+JJo0QANKHRLLRxNy/fGCp/eg5mabi
SfGxa+5K3wtFzYCo49bsHBY9e1f9mjck8TnJDqUPhWreF4kyCiDkSi93lHkqjYu0
+vYLtHdzTjWWcYZr9SsBfsMQURqAN9SypTIzgPgAy3ZeX50uhaZZQp9kAL/vn4Nr
8o2wfG5BuNzVdPcZBHTfab9anzsqZHTzUVds2h9o+qgMiHiPtFMJuSaOvMDCu/gK
Jp01NMY77ACE6s5k19EVxU42WE0Q+QmCEFig5xFjm6xUdIQdFSKx1Gal0Ngg9t0Q
CkOdjOVTWWbFtKWP+D80U996FmRY0xT705E97f123KnQJ64wJ7izdZuEDRy/2bgM
GPCdihQmBZLzf9PnXTpypKvrsoMG36CxSnFMbzSYrCHuPBRf3Ii8QyO3lr5s993A
a+VOAhij6TePp/P18mlL+XUCPV1Y+bAUJTDZpVgP4KbhrrdwkioHEV7KZ2fpK+bu
Wa5696DUqIjMsixBIWxc4FxR88t8AffpPIKu3vgMZV+bxFApXQF9b4R+JppAkZtg
mBxj84mt26tkhlnUkeBqLWx0/f8oAuUhDCCgrdmS7/xPOg29uHhkmG0P0Q0D/+5+
ulh3WcHwC6/v94C8NkKWh8z5RfMSlO81DDCGVY0e8gUOeY4F64eFEKGjQlGqCr6j
ePT0lq3OkSs3W0ih4VV+
=SVE6
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/dt
Merge "STM32 DT updates for v4.6 #2" from Maxime Coquelin:
Highlights:
-----------
- Fix clock references in GPIO nodes
- Add early support to stm32f469 MCU
- Add USB HS support in host mdoe to stm32429-eval board
- Add Ethernet support to stm32429-eval board
* tag 'stm32-dt-for-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: stm32429i-eval: Add USB HS host mode support
ARM: dts: stm32f429: Fix clocks referenced by GPIO banks
ARM: stm32: Supply a DTS file for the STM32F469 Discovery board
- A series of GPMC related interrupt changes from
Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt
support to the NAND driver
- Add RTC support for ti81xx
- Correct LogicPD Torpedo mode description
- Add basic support for LG Optimus Black phone in several
patches by Paul Kocialkowski <contact@paulk.fr>
- Change address-cells for dra7 for LPAE
- Add TBCLK for PWMSS on dra7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1h3JAAoJEBvUPslcq6Vz3sQQALjoT1HdNXPsS9fxoCBMRvcc
ZLMrntfj7QId/uZ63zhSxUqYRZWAGz9paDl43uS6uwWGL7G+Mml8fcpxKR008co2
gKPmAwTIYtfZDq63/mQ38jIkmr4Nj/qvY6COFDz2s5IIv41m2LMEleX5QBs8k/3X
F0FL5A9DYRaVZ5tYmZ64mVcJM/CIdDwyRjhtlV1QHVJrDQVPqcRyZGLuRzQKgati
HG0rUc8/B4ECEryrDK5ZtNqJ5LmpThfyzrjaUMzA8mOBo5HTAOOAkwFTtAxppba9
mHZQgNrJ+nAOShDmb+1wAanWw9s+UtsjKppbOhNdk2QyP4DCX8WIsRPZtp/aiDN8
6+I9mYspffe+uFKrwOpcWqtUk+Dft4P0rbcWGm5Pp+dbfSa94gYoyzHDByP5Lgtv
DOMpEZfqC/uHuhjS3ZIN4EnT2t3mY2aMupWYIWKxjv06X+Cp80XIdB5NVGzGFsqe
5ksvykF75YxMskdyo6egT+2jr+bgRkEs6H76ZHqkc6qTtGxIu6JHiuolOOen8uGH
gk3QbWY6oN6uzwtpcddQkrZkYxeoxOIH9AobHuNQ2MlCE0HwCXNE7U79/fjAv9Zs
dbwkVo5C0fraNG+f2waFskwni3mkUYiUIs8/YXXPLsXKavs9XvL5Wxxz/u7v5c+/
0hdZB8mJuoEtKvmhNk8Z
=JMzE
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Part 2 of device tree changes for omaps for v4.6 merge window" from Tony Lindgren:
- A series of GPMC related interrupt changes from
Rogeq Quadros <rogerq@ti.com> to prepare adding interrupt
support to the NAND driver
- Add RTC support for ti81xx
- Correct LogicPD Torpedo mode description
- Add basic support for LG Optimus Black phone in several
patches by Paul Kocialkowski <contact@paulk.fr>
- Change address-cells for dra7 for LPAE
- Add TBCLK for PWMSS on dra7
* tag 'omap-for-v4.6/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: DRA7: Add dt nodes for PWMSS
ARM: dts: DRA7: Add TBCLK for PWMSS
ARM: dts: DRA7: change address-cells and size-cells
ARM: dts: omap3-sniper: USB OTG support
ARM: dts: LG Optimus Black codename sniper basic support
ARM: dts: dm3730-torpedo-devkit: Add "Wireless" to model
ARM: dts: Add RTC entry for dm816x
ARM: dts: Add RTC entry for dm814x and dra62x
ARM: dts: omap3: Fix NAND device nodes
ARM: dts: dm8168-evm: ARM: dts: Disable wait pin monitoring for NAND
ARM: dts: dm816x: Fix NAND device nodes
ARM: dts: am335x: Disable wait pin monitoring for NAND
ARM: dts: am335x: Fix NAND device nodes
ARM: dts: am437x: Disable wait pin monitoring for NAND
ARM: dts: am437x: Fix NAND device nodes
ARM: dts: dra7: Remove redundant nand property
...
- New i.MX6 board support: NXP/Freescale imx6qp boards, Advantech/GE,
Uniwest evi, Engicam IMX6 Q7, Toradex Apalis SoM and Ixora carrier
boards
- Relicense vf610 dts files under GPLv2/X11
- A patch series from Stefan updating Vybrid Colibri board support with
PMU, regulators and other devices enabled
- Correct PWM pinmux for Ventana boards and add more pinmux for GW54xx
- Clean up imx6q-tbs2910 dts file and add SATA PHY configuration
- A series from Russell cleaning up hummingboard dts files
- A series from Lothar updating Ka-Ro i.MX28, i.MX53 and i.MX6 boards
to use better audio codec frequency and display configurations
- Clean up whitespaces in i.MX6UL pinctrl header and add more devices
support for the SoC
- Other random dts updates to enable various devices
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJW1aZfAAoJEFBXWFqHsHzOWvwH/1ieekZ5VYnGyO4CT39DaNxU
LMkywkPtp8oUfdVHOfGEMj43knYHsaVFakGS2w8iMNzg+YonWXG/mkR3HUJmoS1L
HzFEnapLzACSSCbn8yZzWzzNvAlg2arqFErQUlhXe9/CNz64uZSigsO3Ib/JNOlX
GWDRa8szryEkEyk2cJo/wyWWSkLGGRai4uNBR6BmUq/MltVjVHOvTV5NeyKpinHZ
mQQFGEbvVk1hJ0sfceX/rmdxgvV0H3Axq8C0JyzbevUTcvS45A85tEXHkrHbYb/f
mJCNXxmmt+NrH8x79YxnuhKTRQ8lNn8fBu9wOtMaBJjRNB3ie3HBh2QabXBs/MA=
=FKmy
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt2
Merge "i.MX device tree updates for 4.6" from Shawn Guo:
- New i.MX6 board support: NXP/Freescale imx6qp boards, Advantech/GE,
Uniwest evi, Engicam IMX6 Q7, Toradex Apalis SoM and Ixora carrier
boards
- Relicense vf610 dts files under GPLv2/X11
- A patch series from Stefan updating Vybrid Colibri board support with
PMU, regulators and other devices enabled
- Correct PWM pinmux for Ventana boards and add more pinmux for GW54xx
- Clean up imx6q-tbs2910 dts file and add SATA PHY configuration
- A series from Russell cleaning up hummingboard dts files
- A series from Lothar updating Ka-Ro i.MX28, i.MX53 and i.MX6 boards
to use better audio codec frequency and display configurations
- Clean up whitespaces in i.MX6UL pinctrl header and add more devices
support for the SoC
- Other random dts updates to enable various devices
* tag 'imx-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (75 commits)
ARM: dts: imx53-qsb: Fix gpio button polarity
ARM: dts: vfxxx: Add DAC node for Vybrid SoC
ARM: dts: imx6q: add missing links between ipu2 and mipi dsi
ARM: dts: imx: Add support for Advantech/GE B850v3
ARM: dts: imx: Add support for Advantech/GE B650v3
ARM: dts: imx: Add support for Advantech/GE B450v3
ARM: dts: imx: Add support for Advantech/GE Bx50v3
ARM: dts: imx: Add Advantech BA-16 Qseven module
of: Add vendor prefix for General Electric Company
of: Add vendor prefix for Advantech Corporation
ARM: dts: imx35.dtsi: change the clock information for usb
ARM: dts: imx25.dtsi: change the clock information for usb
ARM: dts: imx6ul: add kpp support
ARM: dts: imx6ul: add gpmi support
ARM: dts: imx6ul: add lcdif support
ARM: dts: imx6ul: add sai support
ARM: dts: imx6ul: add flexcan support
ARM: dts: imx6ul: add sdma support
ARM: dts: imx6ul: add pwm[1-4] nodes
ARM: dts: imx6ul: disable PWMs by default
...
1. Split common reboot/poweroff node to separate DTSI.
2. Don't overheat Odroid XU3 by cooling CPU with cpufreq.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1VvJAAoJEME3ZuaGi4PX0IoP/24addMWJyve/UVCh28cNV0l
gNWhCuVq1bXJIPRNSw+ZOln/XZSjcyuwqU1JNfjz2SsgaaVffPGIioJbKk55qnW7
gUO6vtwO3hxMe1kmAp7cehOep3zSr7YjxvckCmTZVZm/S0skNtsY1YM5M1hqBqi5
yoiozpoUk7LE+4VEYlDhjArwW4qaiQ1PzwD7w+G91zpuRefPiKslWdiOJw0h7BD/
yA0X6rbXC2zjRfKI5kF6dq/bKpWAqweW1FshA4EWG5Tx6jrip2q9qlH5bCl423lc
55mbJYg0YYMBt4I/GQ2oVRnqQulraj2Id2txrXlVbyji9fq7rvJdoMkVjH3CXyod
P7s7FqCgLxd/VVZw9n/Yz8XFlMRvhFMBQ/9ZXm2rpJoRcW3IekIXib23h8kX1I5l
Dd8PCAwmjCRzWCGIaGh1M7JfGDKTXyCrohK+iu78PCJQd0PYkF79Bzc7Ckcsyj/k
P7wzjpwZb83RkSU/VhgpqWxBFICTEyHruLLVCIiTFLyC0CUYOtff9aUYAiWNCQRZ
moLTJr7bqMwuDd0kz/poJ8wdQ+FRZEQfnY64Lxy73L6/lHg9tbHw3tDC7OP3RyWX
QzR3kKrDQdkUp7O+i8YPmQ+AdfnA1cqqds4RlFm+/m6Rm3/7V6d9I1bLy3hgrYcJ
87Zu00PFeuDrDORDhRCY
=P/fL
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Merge "ARM: EXYNOS: dts for 4.6, 2nd pull" from Krzysztof Kozlowski:
Samsung DeviceTree updates and improvements for v4.6, second round:
1. Split common reboot/poweroff node to separate DTSI.
2. Don't overheat Odroid XU3 by cooling CPU with cpufreq.
* tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs
ARM: dts: exynos: Move syscon reboot/poweroff to common dtsi
All PCI mmio ranges are dynamically mapped now, so we
can remove the fixed virtual address definitions.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Instead of using old GPIO API, let's switch to GPIOD API, which
automatically handles polarity.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
In an invalid randconfig build (fixed by another patch),
I ran across this warning:
arch/arm/include/debug/at91.S:18:0: error: "CONFIG_DEBUG_UART_VIRT" redefined [-Werror]
#define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
As Russell pointed out, we should never #define a macro starting
with CONFIG_ in a source file, as that is rather confusing.
This renames the macro to avoid the symbol clash.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Suggested-by: Russell King <linux@arm.linux.org.uk>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add the three leds on the sama5d2 Xplained board with their pinctrl node.
The blue led is positioned with the "heartbeat" trigger.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: add commit message and adapt to newer kernel]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add the push button named "PB USER" with code 0x104. Associated pinctrl node is
also added.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
For USB gadget on port A (device mode):
- pin PA31 is configured as an input GPIO which triggers an interrupt when
vbus is detected on USB port A.
- pin PB9 is configured as an output GPIO and set to low level so the
board doesn't supply vbus to USB port A.
For USB host:
- pin PB10 is configured as an output GPIO and is active at high level.
The ohci driver will activate this pin so the board supplies vbus to USB
port B.
- pin PB9 should be configured as an output GPIO and active at high level
to use to USB port A in host mode (conflicts with USB gadget).
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
MAC is connected to a PHY in MII mode.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Now that the AT24 uses the NVMEM framework, replace the
memory_accessor in the setup() callback with nvmem API calls.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Detailed description for patchset:
1. Add new EXTCON_CHG_USB_SDP type
- SDP (Standard Downstream Port) USB Charging Port
means the charging connector.a
2. Add the VBUS detection by using GPIO on extcon-palmas
- Beaglex15 board uses the extcon-palmas driver
But, beaglex15 board need the GPIO support for VBUS
detection.
3. Fix the minor issue of extcon drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW063aAAoJEJzN3yze689ThbEQAJbn/pHDRlw7u8NUiNfRbQWd
uf//IiF2tbJ8eGpCvYIh+dLSlFbFzn3qIETAXJjZ7NfqYpgZsDAwFoMnVF6FfcMG
o2GAVGnUaXge+s+r5PkIwaCRh9LWO5iHJTHjykonhXaKKO4NrHxtsspo/We6Kth4
kmsrmovWd1CvnsvNZJXFSFf37z2eZFG+RYyrveKhFiTlliqyX/DT/RgOqPPPa0UC
9FBXrQ67ibKymX2qYLb5USQnppNFrnzDCacJBiFc2z/kpFFkII7XDrJVogn2JJfZ
M4uQ8JWqBhjrh2yU1FtQ7vuBfk8/Ssbvbp7J+roHJZGwe6AjVY2d3WCRGMLy/fFh
rCfsVvCrwupPVsVj50yTVyEJ0kiDZ9tz3rboWxfuTv/AtRxpUm9gMZ6yE/g2cBl4
RnkYp9dE/Kmu5BaaJZm9yIlHOEgQD/nhXGWm+BdgJBPB2+qAA0D7VPav0Fazjr8O
fN/kyaFHZ5jxSynGVCTsbfD8cJiVWdRzyxwoeXllvGqxwcdgHzX7LrTXrDkRtgC3
5r1B6qgm0kpPxYotrfPI+vAQnR5PGYBa0L4mwXha1rnonwI39QIgg76ZsHyy6k2u
rwGpT3zQmxFs9puf6pFAGmFCaLd1nb5r7FrslkZsn4gG100Gi0ONRRyN6Jx7f7W2
x/EvDnRYTM/pNpNp04Yb
=Zxas
-----END PGP SIGNATURE-----
Merge tag 'extcon-next-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-testing
Chanwoo writes:
Update extcon for 4.6
Detailed description for patchset:
1. Add new EXTCON_CHG_USB_SDP type
- SDP (Standard Downstream Port) USB Charging Port
means the charging connector.a
2. Add the VBUS detection by using GPIO on extcon-palmas
- Beaglex15 board uses the extcon-palmas driver
But, beaglex15 board need the GPIO support for VBUS
detection.
3. Fix the minor issue of extcon drivers
In the final versions of the Porter board (called "PORTER_C") Renesas
decided to get rid of the Maxim Integrated MAX3355 OTG chip and didn't
add any other provision to differ the host/gadget mode, so we'll have to
remove no longer valid "renesas,enable-gpio" property from the HS-USB
device node. Hopefully, the earlier revisions of the board were never
seen in the wild...
Fixes: c794f6a09a ("ARM: shmobile: porter: add HS-USB DT support")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds support for the volume and gesture keys, using TWL4030 keypad.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This reverts commit 5fcc673067.
The binding may need to change pending related hwmod comments,
so reverting as requested by Paul Walmsley <paul@pwsan.com>.
Let the non boot cpus call into idle with the corresponding hotplug state, so
the hotplug core can handle the further bringup. That's a first step to
convert the boot side of the hotplugged cpus to do all the synchronization
with the other side through the state machine. For now it'll only start the
hotplug thread and kick the full bringup of the cpu.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arch@vger.kernel.org
Cc: Rik van Riel <riel@redhat.com>
Cc: Rafael Wysocki <rafael.j.wysocki@intel.com>
Cc: "Srivatsa S. Bhat" <srivatsa@mit.edu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Turner <pjt@google.com>
Link: http://lkml.kernel.org/r/20160226182341.614102639@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
These patches add RTC support for the AM43xx, and add support for
the DRA7xx eDMA controller's TPCC, TPTC0, and TPTC1 IP blocks.
Also included is a workaround for PRCM hardreset control of the DRA7xx
PCIe subsystem.
Note that I do not have a DRA7xx board, and therefore cannot
test any patches for that SoC family.
Basic build, boot, and PM test logs can be found here:
http://www.pwsan.com/omap/testlogs/omap-hwmod-b-for-v4.6/20160301021258/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW1WdKAAoJEMePsQ0LvSpLoO8P/A05egqdZtbWCte8tK4/E+d1
fdzaev9dC8I6rWlxV6PTFZL8Hw28XtQZDYqV2voRE5nxma1L05Uang2c2tNmO7oH
Qa7pvD/m6vy3A2ZIKgTJeV7Elc5SNEmPQq6/1z1viWni4oUFWrsP1cKPTmUOhTNu
cx6Q2oxkoGlLRmonygJ49da6XShPMIOolDUNfOKFuSmt80RUor2j1Wpu+3wlVZvr
53jSLG8C+RgiUeBT90PUOvI7dAfocOV+G8CnH7/Fnss9+L2skiKwOOUNudGBz3JZ
elAwjyiCkBlo3VGSRk4UarXuzAdCqZqvLSemYZ1JbYT3SbbIWovJ9nX17y7Gl7RT
4KnGW0P+yeYYj9iEwUOs1Yj4DgFTbgkmHqkF2zWPGawjj3AMUKquvYVR1d+Oz3NR
77wdAPIKWWRJ5V8QiQhKiZjpj4TkR7KT1fAF78Kf4eMXwy5tbXUkXyKpj0Izi1Z2
Oe2NHcGOMXbSBYSBK0N9sYXFWKhE3CRkEZ3yoYwTwoDYpDuMWffnRX1a0TGseUb3
xX9j+818/FyKhwEdL4rIHwOYW/iITLUOSUAOt2lnM2xWx3G1aNX7RjreOdobVm7Z
8ZVbX2zFBrP8Fe964ZutoG7FjBqurrOtoJUrZPEPWOcjDMPBi9JfRfwtLzglAnXh
IUglDUxMXscaQulEez3J
=ospe
-----END PGP SIGNATURE-----
Merge tag 'for-v4.6/omap-hwmod-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.6/soc
ARM: OMAP2+: second set of hwmod changes for v4.6
These patches add RTC support for the AM43xx, and add support for
the DRA7xx eDMA controller's TPCC, TPTC0, and TPTC1 IP blocks.
Also included is a workaround for PRCM hardreset control of the DRA7xx
PCIe subsystem.
Note that I do not have a DRA7xx board, and therefore cannot
test any patches for that SoC family.
Basic build, boot, and PM test logs can be found here:
http://www.pwsan.com/omap/testlogs/omap-hwmod-b-for-v4.6/20160301021258/
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] dm814x TRM: SPRUGZ8F: 11.2.4.12.2 NAND Device-Ready Pin
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add Ethernet support (Synopsys MAC IP 3.50a) on stm32f429 SOC.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
The polarity of the gpio buttons is defined to '0' which is
active high. The buttons are active low though which has been verified by
testing it and by looking into the schematics. While at it use
defines rathers than numbers for the key codes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This makes it possible to automatically boot-test this defconfig with
kernelci.org.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Regenerate imx_v4_v5_defconfig by running:
make imx_v4_v5_defconfig
- Manually disable EXT2_FS and EXT3_FS
make savedefconfig
mv defconfig arch/arm/configs/imx_v4_v5_defconfig
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The dmas/dma-names properties are added to the UART nodes. Note that additional
properties are needed to enable them at the board level: check bindings for
details.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
All pinctrl nodes for the Atmel pinctrl controller need to have their
bias configuration explicitly defined. Otherwise, the pinctrl mapping
is not valid.
It works for now as the pinctrl driver proceeds even with invalid
mappings, but this can become an issue, if the pinctrl driver starts
to require valid mappings. Additionally, the pin is not protected from
being remapped later by an other driver.
There is an external 1kOhms pull-up to 3.3V, so no bias is required on
the Ethernet PHY's interrupt line.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
After adding cpufreq-dt support to Exynos542x, the Odroid XU3-Lite can
be easily overheated when launching eight CPU-intensive tasks:
thermal thermal_zone3: critical temperature reached(121 C),shutting down
This seems to be specific to Odroid XU3-Lite board which officially
supports lower frequencies than regular XU3 or XU4. When working at
maximum CPU speed (1800 MHz big and 1300 MHz LITTLE) in warmer place for
longer time, the fan fails to cool down the board and it reaches
critical temperature.
Add CPU cooling to Exynos5422/5800 to fix this issue. When reaching last
interrupt-driven trip-point (70 degrees of Celsius) start passive
cooling in polling mode (slowing CPU by 2 steps). When reaching 85
degrees of Celsius, start slowing even more, down to 600 MHz.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE
and 18 steps for big core (200-1700 MHz). Add respective cooling cells.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and
12 steps for big core (700-1800 MHz). Add respective cooling cells.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
