Commit Graph

23 Commits

Author SHA1 Message Date
Tony Lindgren
46bf4a5622 OMAP voltage layer updates towards supporting auto-retention/auto-off
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Merge tag 'for_3.8-pm-voltage' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-v3.8/pm

OMAP voltage layer updates towards supporting auto-retention/auto-off
2012-11-06 17:06:37 -08:00
Tero Kristo
085b302500 ARM: OMAP3+: vp: use new vp_params for calculating vddmin and vddmax
Now we select the vddmin and vddmax values based on both pmic and
voltage processor data, this allows usage of different power ICs.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 15:13:13 -08:00
Tero Kristo
b254012b21 ARM: OMAP: voltage: renamed vp_vddmin and vp_vddmax fields
These are now called vddmin and vddmax, as these fields will be used
globally for selecting voltage ranges for a pmic channel, and not
only for voltage processor.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 15:03:47 -08:00
Nishanth Menon
f2a0dfefec ARM: OMAP3+: PM: VP: use uV for max and min voltage limits
Every PMIC has it's own eccentricities, For example, one of the
PMIC has MSB set to 1 for a specific function - voltage enable!
using an hardcoded value specific for TWL when copied over to
such an implementation causes the system to crash as the MSB bit
was 0 and the voltage got disabled!.

Instead we use actual values and depend on the convertion routines
to abstract out the eccentricities of each PMIC.

With this, we can now move the voltages to a common location in
voltage.h as they are no longer dependent on PMICs and expect the
PMIC's conversion routines to set a cap if the voltage is out of
reach for the PMIC.

Reported-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 15:03:34 -08:00
Nishanth Menon
9bb053787d ARM: OMAP2+: PM: VP: minor pr_warn updates
change pr_warnings to pr_warn and ensure a newline
is present in all messages

Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-25 14:32:34 -07:00
Paul Walmsley
7852ec0536 ARM: OMAP: unwrap strings
Find and unwrap wrapped strings in the style:

	pr_debug("clockdomain: hardware cannot set/clear wake up of "
		 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);

Keeping these strings contiguous seems to be the current Linux kernel
policy.

The offending lines were found with the following command:

    pcregrep -rnM '"\s*$\s*"' arch/arm/*omap*

While here, some messages have been clarified, some pr_warning(
... calls have been converted to pr_warn( ..., and some printk(KERN_*
... have been converted to pr_*.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-09-12 02:57:10 -06:00
Yuan Jiangli
3223d007a3 ARM: OMAP3+: PM: VP: fix integer truncation error
commit 2f34ce81b8
(OMAP3: PM: Adding voltage driver support.)
introduced runtime computation of waittime to handle all potential
sys clocks available.

In the voltage processor, the SPMSUpdateWait is calculated based on
the slew rate and the voltage step (SMPSUpdateWait = slew rate *
Voltage Step). After the voltage processor receives the SMPS_Ack
signal, the Voltage Controller will wait for SMPSUpdateWait clock
cycles for the voltage to settle to the new value. For all
practical purposes, the waittime parameter is the OMAP hardware
translation of what the slew rate on the PMIC is.

As an example, with TPS62361 on OMAP4460,
step_size = 10000
slew_rate = 32000
sys_clk_rate = 38400

Our current computation results in the following:
 = ((step_size / slew_rate) * sys_clk_rate) / 1000
 = ((10000 / 32000) * 38400 / 1000
 = 0

Fix the same using DIV_ROUND_UP as an extra wait clock cycle
is better than lesser clock cycle. For the above example, this
translates to:
 = (10000 * 38400) / (1000 * 32000)
 = 12

Acked-by: Jon Hunter <jon-hunter@ti.com>
[nm@ti.com: slightly better implementation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Yuan Jiangli <jlyuan@motorola.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-03-06 16:13:50 -08:00
Russell King
d980e0f8d8 ARM: omap: fix oops in arch/arm/mach-omap2/vp.c when pmic is not found
When the PMIC is not found, voltdm->pmic will be NULL.  vp.c's
initialization function tries to dereferences this, which causes an
oops:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT
Modules linked in:
CPU: 0    Not tainted  (3.3.0-rc2+ #204)
PC is at omap_vp_init+0x5c/0x15c
LR is at omap_vp_init+0x58/0x15c
pc : [<c03db880>]    lr : [<c03db87c>]    psr: 60000013
sp : c181ff30  ip : c181ff68  fp : c181ff64
r10: c0407808  r9 : c040786c  r8 : c0407814
r7 : c0026868  r6 : c00264fc  r5 : c040ad6c  r4 : 00000000
r3 : 00000040  r2 : 000032c8  r1 : 0000fa00  r0 : 000032c8
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 80004019  DAC: 00000015
Process swapper (pid: 1, stack limit = 0xc181e2e8)
Stack: (0xc181ff30 to 0xc1820000)
ff20:                                     c0381d00 c02e9c6d c0383582 c040786c
ff40: c040ad6c c00264fc c0026868 c0407814 00000000 c03d9de4 c181ff8c c181ff68
ff60: c03db448 c03db830 c02e982c c03fdfb8 c03fe004 c0039988 00000013 00000000
ff80: c181ff9c c181ff90 c03d9df8 c03db390 c181ffdc c181ffa0 c0008798 c03d9df0
ffa0: c181ffc4 c181ffb0 c0055a44 c0187050 c0039988 c03fdfb8 c03fe004 c0039988
ffc0: 00000013 00000000 00000000 00000000 c181fff4 c181ffe0 c03d1284 c0008708
ffe0: 00000000 c03d1208 00000000 c181fff8 c0039988 c03d1214 1077ce40 01f7ee08
Backtrace:
[<c03db824>] (omap_vp_init+0x0/0x15c) from [<c03db448>] (omap_voltage_late_init+0xc4/0xfc)
[<c03db384>] (omap_voltage_late_init+0x0/0xfc) from [<c03d9df8>] (omap2_common_pm_late_init+0x14/0x54)
 r8:00000000 r7:00000013 r6:c0039988 r5:c03fe004 r4:c03fdfb8
[<c03d9de4>] (omap2_common_pm_late_init+0x0/0x54) from [<c0008798>] (do_one_initcall+0x9c/0x164)
[<c00086fc>] (do_one_initcall+0x0/0x164) from [<c03d1284>] (kernel_init+0x7c/0x120)
[<c03d1208>] (kernel_init+0x0/0x120) from [<c0039988>] (do_exit+0x0/0x2cc)
 r5:c03d1208 r4:00000000
Code: e5ca300b e5900034 ebf69027 e5994024 (e5941000)
---[ end trace aed617dddaf32c3d ]---
Kernel panic - not syncing: Attempted to kill init!

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-02-09 17:56:53 +00:00
Tony Lindgren
4e65331c6b ARM: 7159/1: OMAP: Introduce local common.h files
As suggested by Russell King - ARM Linux <linux@arm.linux.org.uk>,
there's no need to keep local prototypes in non-local headers.

Add mach-omap1/common.h and mach-omap2/common.h and move the
local prototypes there from plat/common.h and mach/omap4-common.h.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-17 17:09:30 +00:00
Kevin Hilman
b666b4767d OMAP3+: VP: combine setting init voltage into common function
combine VPCONFIG init voltage setup into common function and use from
both vp_enable and from vp_forceupdate_scale().

NOTE: this patch changes the sequence of when the initVDD bit is
cleared.  The bit is now cleared immediately after it was written.
Since only the rising edge of this bit has any affect according to the
TRM, the exact timing of clearing of this bit should not have any
effect.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
cc6962dbab OMAP3+: VP: remove unused omap_vp_get_curr_volt()
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
8798c4ab56 OMAP3+: VP: update_errorgain(): return error if VP
Add check for valid VP in omap_vp_update_errorgain()

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Todd Poynor
bea30ed65f OMAP: VP: Explicitly mask VPVOLTAGE field
Reading the VPVOLTAGE field of PRM_VP_*_VOLTAGE registers currently
relies on a u32 -> u8 conversion to mask off the FORCEUPDATEWAIT field
in the upper bits.  Make this explicit using the mask symbol
already defined, added as a new field in struct omap_vp_common.

Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
667216d6a4 OMAP3+: VP: remove omap_vp_runtime_data
Remove the "runtime" VP data in favor of direct programming of VP registers.
The VP is in the PRM, which is in the wakeup powerdomain, so there is no
need to keep the state dynamically.

Fixes to original version from Nishanth Menon <nm@ti.com>

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
76ea7424f8 OMAP3+: VP: create VP helper function for updating error gain
Create new helper function in VP layer for updating VP error gain.
Currently used during pre-scale for VP force update and VC bypass.

TODO: determine if this can be removed from the pre-scale path and
moved to VP enable path.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
6f56727383 OMAP3+: VP: move timing calculation/config into VP init
Move VP timing calcluation (based on sys clock) and register programming
into VP init.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:08 -07:00
Kevin Hilman
0ec3041e91 OMAP3+: VP: struct omap_vp_common: replace shift with __ffs(mask)
In struct omap_vp_common, the shift value can be derived from the mask
value by using __ffs(), so remove the shift value for the various
VPCONFIG bitfields, and use __ffs() in the code for the shift value.

While here, rename field names in kerneldoc comment to match actual
field names in structure.  Also, cleanup indendentaion for other VP
register accesses in omap_vp_init().

No functional changes.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:07 -07:00
Kevin Hilman
633ef8b747 OMAP3+: voltage: remove unneeded debugfs interface
Remove read-only debugfs interface to VP values.  Most of the values
are init-time only and never change.  Current voltage value should be
retreived from the (eventual) regulator framework interface to the
voltage domain.

Fixes to original version provided by Nishanth Menon <nm@ti.com>

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:07 -07:00
Kevin Hilman
b7ea803e55 OMAP3+: VP: cleanup: move VP instance into voltdm, misc. renames
- move VP instance struct from vdd_info into struct voltage domain
- remove _data suffix from structure name
- rename vp_ prefix from vp_common field: accesses are now vp->common
- move vp_enabled bool from vdd_info into VP instance
- remove remaining references to omap_vdd_info

No functional changes.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:09:07 -07:00
Kevin Hilman
ce8ebe0dfb OMAP3+: voltage domain: move PMIC struct from vdd_info into struct voltagedomain
Move structure containing PMIC configurable settings into struct
voltagedomain.  In the process, rename from omap_volt_pmic_info to
omap_voltdm_pmic (_info suffix is not helpful.)

No functional changes.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:08:57 -07:00
Kevin Hilman
4bcc475ebd OMAP3+: voltage: convert to PRM register access functions
Convert VC/VP register access to use PRM VC/VP accessor functions.  In
the process, move the read/write function pointers from vdd_info into
struct voltagedomain.

No functional changes.

Additional cleanup:
- remove prm_mod field from  VC/VP data structures, the PRM register
  access functions know which PRM module to use.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:02:08 -07:00
Kevin Hilman
842ec22852 OMAP3+ VP: replace transaction done check/clear with VP ops
Replace the VP tranxdone check/clear with helper functions from the
PRM layer.

In the process, remove prm_irqst_* voltage structure fields for IRQ
status checking which are no longer needed.

Since these reads/writes of the IRQ status bits were the only PRM
accesses that were not to VC/VP registers, this allows the rest of the
register accesses in the VC/VP code to use VC/VP specific register
access functions (done in the following patch.)

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 12:02:07 -07:00
Kevin Hilman
01f48d308d OMAP2+: voltage: split out voltage processor (VP) code into new layer
This patch is primarily a move of VP specific code from voltage.c into
its own code in vp.c and adds prototypes to vp.h

No functional changes, except debugfs...

VP debugfs moved to 'vp' subdir of <debugfs>/voltage/ and 'vp_'
prefixes removed from all debugfs filenames.

Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-09-15 11:39:11 -07:00