Commit Graph

9 Commits

Author SHA1 Message Date
Lokesh Vutla
3af6ccc3d1 ARM: OMAP: dra7: powerdomain data: Register SoC specific powerdomains
Custom efuse powerdomain is always on in dra72 ES2.0
and dra76 SoCs. So register it as aon for these SoCs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-08-14 10:33:29 -07:00
Nishanth Menon
6b41d44862 ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), with the exception of MPU power domain, all
other power domains do not have memories capable of retention since
they all operate in either "ON" or "OFF" mode. For these power states,
the retention state for memories are basically ignored by PRCM and does
not require to be programmed.

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-06-13 01:04:01 -07:00
Nishanth Menon
9ffb668f26 ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), with the exception of MPU power domain (and
CPUx sub power domains), all other power domains can either operate
in "ON" mode OR in some cases, "OFF" mode. For these power states,
the logic retention state is basically ignored by PRCM and does not
require to be programmed.

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-06-13 01:04:01 -07:00
Nishanth Menon
d16c0d722d ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), L4Per and L3init power domains now operate in
always "ON" mode due to asymmetric aging limitations. Update the same

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-06-13 01:04:01 -07:00
Nishanth Menon
dac4fba2cd ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability
Open Switch Retention(OSWR) is a retention state which is unsupported
in DRA7 SoC. This state is achieved when power state is set to
retention and logic power state is set to OFF.

Even though DRA7 architecture is a OMAP derivative, none of the
powerdomains are actually implemented to achieve OSWR in the SoC.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-13 14:30:10 -07:00
Nishanth Menon
41feb8efd6 ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories
When the power domain is in "ON" state, the memories should be always
in "ON", even though the hardware register allows other states to be
written, wrong states may confuse certain hardware blocks.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-13 14:30:09 -07:00
Nishanth Menon
f971512c78 ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.

By allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues and device failure as a result.

Ref: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-13 14:30:09 -07:00
Nishanth Menon
cafc8cb5b9 ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate
DRA7 supports only CSWR for CPU, MPU power domains. Core power domain
supports upto INA.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-09-08 11:22:31 -05:00
Ambresh K
97dd16b190 ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update header
Add the data file to describe all power domains inside the DRA7XX SoC.

Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23 04:28:36 -06:00