Pull networking updates from David Miller:
"Highlights:
1) Support TX_RING in AF_PACKET TPACKET_V3 mode, from Sowmini
Varadhan.
2) Simplify classifier state on sk_buff in order to shrink it a bit.
From Willem de Bruijn.
3) Introduce SIPHASH and it's usage for secure sequence numbers and
syncookies. From Jason A. Donenfeld.
4) Reduce CPU usage for ICMP replies we are going to limit or
suppress, from Jesper Dangaard Brouer.
5) Introduce Shared Memory Communications socket layer, from Ursula
Braun.
6) Add RACK loss detection and allow it to actually trigger fast
recovery instead of just assisting after other algorithms have
triggered it. From Yuchung Cheng.
7) Add xmit_more and BQL support to mvneta driver, from Simon Guinot.
8) skb_cow_data avoidance in esp4 and esp6, from Steffen Klassert.
9) Export MPLS packet stats via netlink, from Robert Shearman.
10) Significantly improve inet port bind conflict handling, especially
when an application is restarted and changes it's setting of
reuseport. From Josef Bacik.
11) Implement TX batching in vhost_net, from Jason Wang.
12) Extend the dummy device so that VF (virtual function) features,
such as configuration, can be more easily tested. From Phil
Sutter.
13) Avoid two atomic ops per page on x86 in bnx2x driver, from Eric
Dumazet.
14) Add new bpf MAP, implementing a longest prefix match trie. From
Daniel Mack.
15) Packet sample offloading support in mlxsw driver, from Yotam Gigi.
16) Add new aquantia driver, from David VomLehn.
17) Add bpf tracepoints, from Daniel Borkmann.
18) Add support for port mirroring to b53 and bcm_sf2 drivers, from
Florian Fainelli.
19) Remove custom busy polling in many drivers, it is done in the core
networking since 4.5 times. From Eric Dumazet.
20) Support XDP adjust_head in virtio_net, from John Fastabend.
21) Fix several major holes in neighbour entry confirmation, from
Julian Anastasov.
22) Add XDP support to bnxt_en driver, from Michael Chan.
23) VXLAN offloads for enic driver, from Govindarajulu Varadarajan.
24) Add IPVTAP driver (IP-VLAN based tap driver) from Sainath Grandhi.
25) Support GRO in IPSEC protocols, from Steffen Klassert"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1764 commits)
Revert "ath10k: Search SMBIOS for OEM board file extension"
net: socket: fix recvmmsg not returning error from sock_error
bnxt_en: use eth_hw_addr_random()
bpf: fix unlocking of jited image when module ronx not set
arch: add ARCH_HAS_SET_MEMORY config
net: napi_watchdog() can use napi_schedule_irqoff()
tcp: Revert "tcp: tcp_probe: use spin_lock_bh()"
net/hsr: use eth_hw_addr_random()
net: mvpp2: enable building on 64-bit platforms
net: mvpp2: switch to build_skb() in the RX path
net: mvpp2: simplify MVPP2_PRS_RI_* definitions
net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
net: mvpp2: remove unused register definitions
net: mvpp2: simplify mvpp2_bm_bufs_add()
net: mvpp2: drop useless fields in mvpp2_bm_pool and related code
net: mvpp2: remove unused 'tx_skb' field of 'struct mvpp2_tx_queue'
net: mvpp2: release reference to txq_cpu[] entry after unmapping
net: mvpp2: handle too large value in mvpp2_rx_time_coal_set()
net: mvpp2: handle too large value handling in mvpp2_rx_pkts_coal_set()
net: mvpp2: remove useless arguments in mvpp2_rx_{pkts, time}_coal_set
...
Pull pin control updates from Linus Walleij:
"Pin control bulk changes for the v4.11 kernel cycle.
Core changes:
- Switch the generic pin config argument from 16 to 24 bits, only use
8 bits for the configuration type. We might need to encode more
information about a certain setting than we need to encode
different generic settings.
- Add a cross-talk API to the pin control GPIO back-end, utilizing
pinctrl_gpio_set_config() from GPIO drivers that want to set up a
certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the GPIO chips,
so that they pass a generic configuration for things like
debouncing and single ended (typically open drain). This change has
also been merged in an immutable branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing a pin
controller before trying to get any hogs.
- For pin controllers putting all group and function definitions into
the device tree, we now have generic code to deal with this and it
is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down. New
subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in the
LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode. STM32H743 MCU
support.
- Allwinner sunxi: deep simplifications on how to support subvariants
of SoCs without adding to much SoC-specific data for each
subvariant, especially for sun5i variants. New driver for V3s SoCs.
New driver for the H5 SoC. Support A31/A31s variants with the new
variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction. New
subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
driver to access regmaps. Add infrastructure for pin-bank retention
control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm driver
realtime-safe"
* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
pinctrl: intel: unlock on error in intel_config_set_pull()
pinctrl: berlin: make bool drivers explicitly non-modular
pinctrl: spear: make bool drivers explicitly non-modular
pinctrl: mvebu: make bool drivers explicitly non-modular
pinctrl: sunxi: make sun5i explicitly non-modular
pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
pinctrl: samsung: mark PM functions as __maybe_unused
pinctrl: sunxi: Remove redundant A31s pinctrl driver
pinctrl: sunxi: Support A31/A31s with pinctrl variants
pinctrl: Amend bindings for STM32 pinctrl
pinctrl: Add STM32 pinctrl driver DT bindings
pinctrl: stm32: Add STM32H743 MCU support
include: dt-bindings: Add STM32H7 pinctrl DT defines
gpio: aspeed: Remove dependence on GPIOF_* macros
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
drivers: pinctrl: add driver for Allwinner H5 SoC
pinctrl: intel: Add Intel Gemini Lake pin controller support
pinctrl: intel: Add support for 1k additional pull-down
pinctrl: intel: Add support for hardware debouncer
...
Pull hwmon updates from Guenter Roeck:
- new driver for stts751
- it87: Added support for IT8622E and IT8792E; improved support for
other chips
- lm70: Added support for TMP122/124
- use permission-specific DEVICE_ATTR variants where possible
- fixed overflows in various drivers
- minor improvements in various drivers
* tag 'hwmon-for-linus-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: (95 commits)
hwmon: (sht15) Add device tree support
devicetree: add lm90 thermal_zone sensor support
hwmon: (it87) Add support for IT8792E
hwmon: (it87) Do not overwrite bit 2..6 of pwm control registers
hwmon: (it87) Fix pwm4 detection for IT8620 and IT8628
hwmon: (it87) Ensure that pwm control cache is current before updating values
hwmon: (it87) Improve IT8622 support
hwmon: (it87) Add support for IT8622E
hwmon: (it87) Add feature flag indicating that VIN3 is connected to 5V
DT: add binding documentation for STTS751
hwmon: new driver for ST stts751 thermal sensor
hwmon: Register thermal zone only if 'dev' parameter was provided
hwmon: Relax name attribute validation for new APIs
hwmon: Update documentation to clarify rules for the 'name' attribute
hwmon: Make name attribute mandatory for new APIs
hwmon: (lm70) Add support for TI TMP122/124
hwmon: (lm70) Utilize dev_warn instead of pr_warn
hwmon: (ltc4151) Export OF device ID table as module aliases
hwmon: (adc128d818) Preserve operation mode
hwmon: (adc128d818) Support operation modes 1-3
...
Pull "Samsung DeviceTree ARM64 update for v4.11, third round" from Krzysztof Kozłowski:
1. Add necessary initial configuration for clocks of display subsystem.
Till now it worked mostly thanks to bootloader.
2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7.
3. Enable USB 3.0 (DWC3) on Exynos7.
* tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (27 commits)
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
arm64: dts: exynos: set LDO7 regulator as always on
arm64: dts: exynos: configure TV path clocks for Ultra HD modes
arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs
arm64: dts: exynos: Add TM2 touchkey node
arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes
arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
arm64: dts: exynos: Add HDMI node to Exynos5433
arm64: dts: exynos: Add DECON_TV node to Exynos5433
arm64: dts: exynos: Fix addresses in node names on Exynos5433
arm64: dts: exynos: Make TM2 and TM2E independent from each other
arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
...
This patch updates the LM90's devicetree definition to
include the #thermal-sensor-cells property as well as
the sensor constants in include/dt-bindings/thermal/lm90.h.
Cc: Wei Ni <wni@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.
LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get
from Device Tree.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull Rockchip clk updates from Heiko Stuebner:
"Non-critical fix for the pclk_edp divider on rk3399, one new
clock-id and making niu (interconnect) clocks critical on
rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running
all the time when more users access particular clock subtrees."
* tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3288: make all niu clocks critical
clk: rockchip: use rk3288 vip_out clock ids
clk: rockchip: add rk3288 vip_out clock id
clk: rockchip: fix the incorrect pclk_edp div width for RK3399
Pull Allwinner clock updates from Maxime Ripard:
- Support for one new SoC, the V3s
- Conversion of two old SoCs to the new framework, the old sun5i family
and the A80
- A bunch of fixes
* tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
ARM: dts: sun9i: Switch to new clock bindings
clk: sunxi-ng: Add A80 Display Engine CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU
clk: sunxi-ng: Call divider_round_rate if we only have a single parent
ARM: gr8: Convert to CCU
ARM: sun5i: Convert to CCU
clk: sunxi-ng: Add sun5i CCU driver
clk: sunxi-ng: Implement global pre-divider
clk: sunxi-ng: Implement multiplier maximum
clk: sunxi-ng: mult: Fix minimum in round rate
clk: sunxi-ng: Implement factors offsets
clk: sunxi-ng: multiplier: Add fractional support
clk: sunxi-ng: add support for V3s CCU
dt-bindings: add device binding for the CCU of Allwinner V3s
...
Exynos7 SoC pinctrl configurations are similar to existing Exynos4/5 except
for FSYS1 pinctrl drive strengths. So adding Exynos7 specific FSYS1 blocks
pinctrl driver strength related macros which will be used in Exynos7
DTSi files.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.
One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.
Add support for the display engine clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.
Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ZTE PM domain driver support for 4.11:
- It includes a series which adds DT bindings and PM domain driver for
PCU (Power Control Unit) block found on ZTE ZX2967 family SoC.
* tag 'zte-pd-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: zte: pm_domains: Add support for zx296718
soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family
soc: zte: Add header for PM domains specifiers
MAINTAINERS: add zx2967 SoC drivers to ARM ZTE architecture
dt-bindings: zte: add bindings document for zx2967 power domain controller
Signed-off-by: Olof Johansson <olof@lixom.net>
Second Round of Renesas ARM Based SoC DT Updates for v4.11
Enhancements:
- Add power-domains to mmcif on r7s72100 SoC
- Add OSTM to rskrza1/r7s72100
- Link ARM GIC to clock and clock domain on r8a774[35] SoCs
Clean-up:
- Correct SATA device status on r8a7779/marzen
* tag 'renesas-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r7s72100: add power-domains to mmcif
ARM: dts: rskrza1: add ostm DT support
ARM: dts: r7s72100: add ostm to device tree
ARM: dts: r7s72100: add ostm clock to device tree
ARM: dts: r8a7745: Link ARM GIC to clock and clock domain
ARM: dts: r8a7743: Link ARM GIC to clock and clock domain
ARM: dts: r8a7779, marzen: Fix sata device status
Signed-off-by: Olof Johansson <olof@lixom.net>
Some extensions to the power-domain driver to support domains in
hiword registers (write-mask in upper 16bit) and domain-definitions
for the rk3328 soc.
Secondly a "driver" that attaches to the already existing grf nodes
and is able to set static defaults for settings that cannot really
be attached to any specific subsystem.
Most GRF settings can already be set from drivers using them, but there
are some behavioural settings like the mmc/jtag switch that cannot.
As the commit message states this is really meant as a last line
of defence for things that neither belong to a subsystem nor to the
Having this here allows arm64 socs to have this as well and also
moves another bit of code out of the arm32 mach-rockchip.
* tag 'v4.11-armsoc-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: drop rk3288 jtag/mmc switch handling
soc: rockchip: add driver handling grf setup
dt-bindings: add used but undocumented rockchip grf compatible values
soc: rockchip: power-domain: add power domain support for rk3328
dt-bindings: add binding for rk3328 power domains
dt-bindings: power: add RK3328 SoCs header for idle-request
soc: rockchip: power-domain: Support domain control in hiword-registers
Signed-off-by: Olof Johansson <olof@lixom.net>
AHB clock branch is needed in order to enable SDHCI
on msm899(2/4).
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY
- Exynos PLL code updates and overall minor clean-ups
* tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: mark s3c...._clk_sleep_init() as __init
clk: samsung: Add enable/disable support for PLL35XX clocks
clk: samsung: exynos5433: Correct typos in SoC name
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk-ux500:
clk: ux500: Convert ABx500 clocks to use OF probing
clk: ux500: Add device tree bindings for ABx500 clocks
clk: ux500: move AB8500 sysclk over to PRCMU clk driver
These clocks have been broken for a long time unfortunately, a
hurdle of misc problems made them stop working at some point
breaking USB and audio on Ux500.
The platform as such and all "regular" clocks are migrated to
OF/device tree, so let's migrate also this driver.
With this patch and the corresponding DTS fixes, and a bunch
of probe deferral fixes, audio starts working again on Ux500.
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same
silicon, and all share the same clocks.
However, they're not packaged in the same way, and therefore not all the
controllers are actually available on all these SoCs.
Introduce a clock controller driver for all these SoCs with different
compatibles to take that into account.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver. In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull Rockchip clk updates from Heiko Stuebner:
A new clock-type for the 1-2 muxes per soc that are for whatever reason
controlled through the General Register Files, support for the rk3328
clock-controller (including a new pll-type) and the usual clock ids and
some fixes.
* tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: clk: add rockchip,grf property for RK3399
clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: use rk3288 isp_in clock ids
clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: add rk3288 isp_in clock ids
clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER
clk: rockchip: add clock controller for rk3328
dt-bindings: add bindings for rk3328 clock controller
clk: rockchip: add dt-binding header for rk3328
clk: rockchip: add new pll-type for rk3328
clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288
clk: rockchip: add a clock-type for muxes based in the grf
Pull Samsung clk updates from Sylwester Nawrocki:
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
* tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)
clk: samsung: exynos-audss: Replace syscore PM with platform device PM
clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks
about CSI, are different, which makes it to need a new CCU driver.
Add such a new driver for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Samsung DeviceTree ARM64 update for v4.11:
1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with
necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433).
2. Use macros for pinctrl settings on Exynos5433.
This contains necessary header with bindings.
3. Minor cleanups in Exynos5433 DTSI and boards using it.
4. Create common DTSI betweem Exynos5433 TM2E and TM2E.
5. Add HDMI/TV to Exynos5433 TM2.
* tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
arm64: dts: exynos: Add HDMI node to Exynos5433
arm64: dts: exynos: Add DECON_TV node to Exynos5433
arm64: dts: exynos: Fix addresses in node names on Exynos5433
arm64: dts: exynos: Make TM2 and TM2E independent from each other
arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E
arm64: dts: exynos: Comply to the samsung pinctrl naming convention in TM2
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos5433
pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433
arm64: dts: exynos: Add support of bus frequency using VDD_INT on Exynos5433 TM2
arm64: dts: exynos: Add bus nodes using VDD_INT for Exynos5433
arm64: dts: exynos: Add PPMU node to Exynos5433
Signed-off-by: Olof Johansson <olof@lixom.net>
Support for Exynos4415 is going away because there are no internal nor
external users.
Since commit 46dcf0ff0d ("ARM: dts: exynos: Remove exynos4415.dtsi"),
the platform cannot be instantiated so remove also the drivers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds header with values used for ZTE 2967
SoC's power domain driver.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index 1 to use these clocks in DT.
e.g. <&rcc 1 CLK_LSI>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
