Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
Some IXP4xx SoC and driver related changes for v5.17:
- Drop unused Kconfig options
- Drop unused platform data header file
* tag 'ixp4xx-arm-soc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h
ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X
Link: https://lore.kernel.org/r/CACRpkdZXZBpexMUuwTV-RB7_QAjBQkSbRsaBtgFShcqxuNTUgw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The "pwm-" prefix currently matches the DT schema for PWM controllers
and throws an error in that case. This is something that should be fixed
in the PWM DT schema, but in this case we can also preempt any such
conflict by naming the nodes after the pins like we do for many others
of these nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra124, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement. Reorganize CPU and EMC OPP table device-tree nodes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When the Tegra High-Speed UART is used instead of the regular UART, the
reg-shift property is implied from the compatible string and should not
be explicitly listed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to be able to pass DT schema validation, change the GPU nodes'
unit-address to the standard notation. Previously this was using a "0,"
prefix that originated from a time when the top-level device tree node
contained #address-cells = <2>.
Note that this technically breaks backwards-compatibility with certain
older versions of the U-Boot bootloader because early versions used a
hard-coded DT path lookup to find the GPU node and perform some fixups
on it. However, this was changed to a compatible string based lookup in
April 2016, so it's reasonable to expect people to update U-Boot on the
systems that they want to use this updated kernel DTB with.
Signed-off-by: Thierry Reding <treding@nvidia.com>
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra memory controller provides reset controls for hotflush reset,
so the #reset-cells property must be specified.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The TKE (time-keeping engine) found on Tegra114 and later is no longer
backwards compatible with the version found on Tegra20, so update the
compatible string list accordingly.
Note that while the hardware block is strictly backwards-compatible, an
architectural timer exists on those newer SoCs that is more reliable, so
that should always be preferred.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
[treding@nvidia.com: factored out patch and wrote commit message]
Signed-off-by: David Heidelberg <david@ixit.cz>
Co-developed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
[treding@nvidia.com: factored out patch and wrote commit message]
Signed-off-by: David Heidelberg <david@ixit.cz>
Co-developed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PMIC found on Dalmore, TN7 and Roth is a TPS65913, so add the
specific compatible string in addition to the generic Palmas series
compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The external memory controller should be sorted after the memory
controller to keep the ordering by unit-address intact.
Signed-off-by: Thierry Reding <treding@nvidia.com>
IXP4xx DTS changes for v5.17:
- Add the LEDs to the Freecom FSG-3 that were missing.
- Add a devicetree for the Gorami MultiLink Router
- Add a devicetree for the Gateway GW7001 Router
This completes the migration of all IXP4xx devices to
device tree files.
Next merge window we will delete the remaining board files,
it cannot be done now because of cross-tree dependencies.
* tag 'ixp4xx-dtx-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ixp4xx: Add devicetree for Gateway 7001
ARM: dts: Add Goramo MultiLink device tree
ARM: dts: Add FSG3 system controller and LEDs
Link: https://lore.kernel.org/r/CACRpkdYiWK7TEbZrh4_0WT5obMk=ZSc7AQVUSPXL+-uZ_hsUEA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The nxp,imx7-mipi-csi2.yaml binding requires ports to be grouped in a
ports node, as multiple ports are present. Fix imx7s.dtsi and the only
board file that references the mipi_csi ports.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The reset-names property isn't defined by the nxp,imx7-mipi-csi2.yaml
binding, and isn't used by the corresponding driver as it acquires the
reset with a NULL ID. Drop it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The fsl,csis-hs-settle property isn't defined by the
nxp,imx7-mipi-csi2.yaml binding, and isn't parsed by the corresponding
driver. Drop it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With the updated dt-bindings for the spba-bus, rename spba@xxxx
to spba-bus@xxxx. There are no functional changes.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
AT91 DT #1 for 5.17:
- 2 low priority fixes about pin function for sama7g5 and better
tailored mmc interface on sama5d2 xplained
- Addition of the Microchip EVB-KSZ9477: a Gigabit Ethernet
managed Switch Evaluation Board
- QSPI: addition of sama5d2 clock name and nodes for new sama7g7 and its
associated Evaluation Kit
* tag 'at91-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5ek: Add QSPI0 node
ARM: dts: at91: sama7g5: Add QSPI nodes
ARM: dts: at91: sama5d2: Name the qspi clock
ARM: dts: at91: add Microchip EVB-KSZ9477 board
ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl
ARM: dts: at91: update alternate function of signal PD20
Link: https://lore.kernel.org/r/20211213161451.90786-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The DragonBoard 410c is a convenient device for testing and debugging.
Since there is support for using ARM32 kernels on MSM8916 now, also
build the DB410c DTB on ARM32 so it can be used for testing. ARM64
is still the main supported architecture for DB410c but it actually
works great on ARM32 as well.
The "apq8016-sbc.dts" is simply included as-is from ARM64 similar
to the approach used for Raspberry Pi (e.g. bcm2711-rpi-4-b.dts).
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211213113250.4249-1-stephan@gerhold.net
Steven Maddox reported in the OpenWrt bugzilla, that his
RaidSonic IB-NAS4220-B was no longer booting with the new
OpenWrt 21.02 (uses linux 5.10's device-tree). However, it was
working with the previous OpenWrt 19.07 series (uses 4.14).
|[ 5.548038] No RedBoot partition table detected in 30000000.flash
|[ 5.618553] Searching for RedBoot partition table in 30000000.flash at offset 0x0
|[ 5.739093] No RedBoot partition table detected in 30000000.flash
|...
|[ 7.039504] Waiting for root device /dev/mtdblock3...
The provided bootlog shows that the RedBoot partition parser was
looking for the partition table "at offset 0x0". Which is strange
since the comment in the device-tree says it should be at 0xfe0000.
Further digging on the internet led to a review site that took
some useful PCB pictures of their review unit back in February 2009.
Their picture shows a Spansion S29GL128N11TFI01 flash chip.
>From Spansion's Datasheet:
"S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors"
Steven also provided a "cat /sys/class/mtd/mtd0/erasesize" from his
unit: "131072".
With the 128 KiB Sector/Erasesize in mind. This patch changes the
fis-index-block property to (0xfe0000 / 0x20000) = 0x7f.
Fixes: b5a923f8c7 ("ARM: dts: gemini: Switch to redboot partition parsing")
Reported-by: Steven Maddox <s.maddox@lantizia.me.uk>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Steven Maddox <s.maddox@lantizia.me.uk>
Link: https://lore.kernel.org/r/20211206004334.4169408-1-linus.walleij@linaro.org'
Bugzilla: https://bugs.openwrt.org/index.php?do=details&task_id=4137
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
