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2 Commits

Author SHA1 Message Date
Dinh Nguyen
c0a636e4cc clk: socfpga: stratix10: fix rate calculation for pll clocks 
The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-01-11 15:41:02 -08:00
Dinh Nguyen
07afb8db73 clk: socfpga: stratix10: add clock driver for Stratix10 platform 
Add a clock driver for the Stratix10 SoC. The driver is similar to the
Cyclone5/Arria10 platforms, with the exception that this driver only uses
one single clock binding.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2018-04-06 10:12:35 -07:00