From Kukjin Kim:
Here is Samsung fixes for v3.7 and it is for fixing of mdma1 address
for exynos4210 rev0 SoC.
* 'v3.7-samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: PL330 MDMA1 fix for revision 0 of Exynos4210 SOC
Signed-off-by: Olof Johansson <olof@lixom.net>
The armada_cfg_base() function returns the base address of the
registers that allow to configure the decoding for a particular
address window. On Armada 370/XP, the lower windows have more
configuration registers (4 registers) than the higher windows (2
registers). This armada_cfg_base() takes this into account by doing a
different offset calculation depending on the window number, but this
offset calculation was wrong for the higher windows.
Even though we were not using high window numbers until now (only
window 0 is used to map the BootROM, needed for SMP), we use this
function at boot time to disable all windows to ensure that nothing
remains intialized from what the bootloader has done.
Unfortunately, the U-Boot on the OpenBlocks AX3-4 uses a window with a
high number (above 8) to remap the BootROM. And then when the kernel
boots, it remaps the BootROM in window 0. Normally, this is not a
problem, because all windows have previously been disabled. Except
that due to our wrong offset calculation, the windows with high
numbers were not properly disabled, leading to the BootROM being
mapped twice. The visible result of this bug was that the kernel was
unable to get the second CPU started on the OpenBlocks AX3-4
platform. With this fix, all windows are properly cleared at boot
time, the BootROM is remapped only once in window 0, and the second
CPU boots fine.
Thanks a lot to Lior Amsamlen <alior@marvell.com> for his help in
debugging this problem.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
Strictly speaking, this bug was introduced in 3.7, but since the only
platforms supported in 3.7 were Armada 370 and Armada XP, and there
was anyway no SMP support at this time, it isn't really worth the
effort to push this patch in 3.7.
Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:
> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
> • Ref_PCIe = 125 MHz
> • Ref_SATA = 100 MHz
> • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Set "y_skip_top" to zero and revise comment as I do not see this line
corruption on two different mt9v022 setups. The first read-out line
is perfectly fine. Add mt9v022 platform data configuring y_skip_top
for platforms that have issues with the first read-out line. Set
y_skip_top to 1 for pcm990 board.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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Merge tag 'marvell-armadaxp-smp-for-3.8' of github.com:MISL-EBU-System-SW/mainline-public into mevbu-dt-additions
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
Conflicts:
arch/arm/mach-mvebu/armada-370-xp.c
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for Plat'Home OpenBlocks A6 using the device tree
where possible.
This commit supports SATA, USB, ether and serial console.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds initial dts file for EXYNOS5440 SoC and adds the
dts file for SSDK5440 board which is a kind of reference board.
More properties will be added later.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The ixp4xx queue manager uses "const struct qmgr_regs __iomem *" as the
type for a pointer that is passed to __raw_writel, which is not
allowed because of the const-ness.
Dropping the 'const' keyword fixes the problem. While we're here,
let's also drop the useless type cast.
Without this patch, building ixp4xx_defconfig results in:
In file included from arch/arm/mach-ixp4xx/ixp4xx_qmgr.c:15:0:
arch/arm/mach-ixp4xx/include/mach/qmgr.h: In function 'qmgr_put_entry':
arch/arm/mach-ixp4xx/include/mach/qmgr.h:96:2: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default]
arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *'
In file included from drivers/net/ethernet/xscale/ixp4xx_eth.c:41:0:
arch/arm/mach-ixp4xx/include/mach/qmgr.h: In function 'qmgr_put_entry':
arch/arm/mach-ixp4xx/include/mach/qmgr.h:96:2: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default]
arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *'
arch/arm/mach-ixp4xx/ixp4xx_qmgr.c: In function 'qmgr_set_irq':
arch/arm/mach-ixp4xx/ixp4xx_qmgr.c:41:9: warning: passing argument 2 of '__raw_writel' discards 'const' qualifier from pointer target type [enabled by default]
arch/arm/include/asm/io.h:88:91: note: expected 'volatile void *' but argument is of type 'const u32 *'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
It doesn't make much sense to map QMgr dynamically - we almost always need it
and the static mapping will be needed for little-endian data-coherent operation
(to make QMgr region value-coherent).
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Merge tag 'marvell-openblocks-i2c-sata-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell SATA and I2C enabling for OpenBlocks AX3-4
When booting with DT the OF core can fill up the resources provided within
the DT blob.
The current way of handling the DT boot prevents us from removing hwmod data
for platforms only suppose to boot with DT (OMAP5 for example) since we need
to keep the whole hwmod database intact in order to have more resources in
hwmod than in DT (to be able to append the DMA resource from hwmod).
To fix this issue we just examine the OF provided resources:
If we do not have resources we use hwmod to fill them.
If we have resources we check if we already able to recive DMA resource, if
no we only append the DMA resurce from hwmod to the OF provided ones.
In this way we can start removing hwmod data for devices which have their
resources correctly configured in DT without regressions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Benoît Cousson <b-cousson@ti.com>
[paul@pwsan.com: fixed checkpatch problem; updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add flags parameter for omap_hwmod_count_resources() so users can tell which
type of resources they are interested when counting them in hwmod database.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Benoît Cousson <b-cousson@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP4 has module specific context lost registers which makes it now
possible to have module level context loss count, instead of relying
on the powerdomain level context count.
Add 2 private hwmod api's to update/clear the hwmod/module specific
context lost counters/register.
Update the module specific context_lost_counter and clear the hardware
bits just after enabling the module.
omap_hwmod_get_context_loss_count() now returns the hwmod context loss
count them on platforms where they exist (OMAP4), else fall back on
the pwrdm level counters for older platforms.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added function kerneldoc, fixed structure kerneldoc,
rearranged structure to avoid memory waste, marked fns as OMAP4-specific,
prevent fn entry on non-OMAP4 chips, reduced indentation, merged update
and clear, merged patches]
[t-kristo@ti.com: added support for arch specific hwmod ops, and changed
the no context offset indicator to USHRT_MAX]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: use NO_CONTEXT_LOSS_BIT flag rather than USHRT_MAX;
convert unsigned context lost counter to int to match the return type;
get rid of hwmod_ops in favor of the existing soc_ops mechanism;
move context loss low-level accesses to the PRM code]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some PRM functions will need to be called by the hwmod code early in
kernel init. To handle this, split the PRM initialization code into
early and late phases. The early init is handled via mach-omap2/io.c,
while the late init is handled by subsys_initcall().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Now that we have support for the I2C busses on Armada 370/XP, and
support for the RTC on the OpenBlocks AX3-4 platform, include the
necessary options in mvebu_defconfig.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This patch enables SATA support on the OpenBlocks AX3-4. It has one
internal SATA port, and an external eSATA port.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The OpenBlocks AX3-4 has a Seiko Instruments S-35390A as the RTC
controller. This patch enables this RTC device in the OpenBlocks
AX3-4 Device Tree.
[Thomas Petazzoni: updated with other OpenBlocks changes, rephrased
commit log.]
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The OpenBlocks AX3-4 board, based on the Armada XP SoC, has an I2C
bus. This patch enables this bus and sets the clock frequency of the
bus.
[Thomas Petazzoni: updated with other changes on OpenBlocks, rephrased
commit log.]
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The Armada 370 and Armada XP have the same I2C controllers as previous
Marvell SoCs, so the existing mv64xxx-i2c driver works fine.
[Thomas Petazzoni: updated on top of other Armada 370/XP changes,
rephrased the commit log].
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
essential pins.
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Merge tag 'omap-for-v3.7-rc5/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From Tony Lindgren:
Few more regression fixes related to u-boot only muxing
essential pins.
* tag 'omap-for-v3.7-rc5/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC
ARM: OMAP3: igep0020: Set WIFI/BT GPIO pins in correct mux mode
ARM: OMAP: Add maintainer entry for IGEP machines
It has been a while since dove_defconfig was updated to recent development.
This patch adds all currently available Dove boards, including a DT-enabled
machine.
DT support requires to allow ATAGS passed by boot loader as most of them are
not yet capable of passing DT blobs. Also OF_SERIAL is enabled to actually
see the bootlog.
Finally, sdhci driver for Dove, mv_cesa, GPIO LEDs, and highmem support is
added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code) have enabled the
pendown GPIO debounce time setting by the below sequence:
gpio_request_one()
gpio_set_debounce()
gpio_free()
It also revealed a bug in the OMAP GPIO handling code which prevented
the GPIO debounce clock to be disabled and CORE transition to low power
states.
Commit c9c55d9 (gpio/omap: fix off-mode bug: clear debounce settings on
free/reset) fixes the OMAP GPIO handling code by making sure that the
GPIO debounce clock gets disabled if no GPIO is requested from current
bank.
While fixing the OMAP GPIO handling code (in the right way), the above
commit makes the gpio_request->set_debounce->free sequence invalid as
after freeing the GPIO, the debounce settings are lost.
Fix the debounce settings by moving the debounce initialization to the
actual GPIO requesting code - the ads7846 driver.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested by: Maxime Hadjinlian <mhadjinlian@lacie.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the 'LaCie Ethernet Disk mini v2' board to the
Device Tree. All devices that have existing Device Tree bindings are
converted over to the Device Tree, the other devices remain
instantiated in the old way, until the respective drivers get the
needed Device Tree bindings.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested by: Maxime Hadjinlian <mhadjinlian@lacie.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds basic DT support for the Orion5x SoC family. It adds
an orion5x.dtsi description of the Orion5x SoC as well as the needed
DT_MACHINE structure to support boards converted to DT in the future.
So far, the Device Tree contains the interrupt controller, the GPIO
bank, the UART controllers, the SPI controller, the watchdog, the SATA
controller, the I2C controller and the cryptographic engine.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested by: Maxime Hadjinlian <mhadjinlian@lacie.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is a simple mechanical update of the orion5x_defconfig
file to the current kernel (i.e, just 'make orion5x_defconfig; make
savedefconfig'). Doing this update allows to more easily separate
DT-related configuration changes in the following patches.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested by: Maxime Hadjinlian <mhadjinlian@lacie.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Hello, Andrew
> > +#define NSA310_GPIO_LED_ESATA_GREEN 12
> > <..>
> > +#define NSA310_GPIO_POWER_OFF 48
>
> It looks like most of these are not used. Please remove them.
True. Fixed.
> > +static struct mtd_partition nsa310_mtd_parts[] = {
> > + {
> > + .name = "uboot",
> > + .offset = 0,
> > + .size = 0x100000,
> > + .mask_flags = MTD_WRITEABLE,
> > + }, {
> > <..>
> You should be able to put all that into DT. Take a look at
Correct. I did the conversion and tested that the partitions
can be read with dd and produce exactly the same data before and
after conversion. So, the partition offsets at least should be fine.
> > +static struct i2c_board_info __initdata nsa310_i2c_info[] = {
> > + { I2C_BOARD_INFO("adt7476", 0x2e) },
> > +};
>
> You can also do this in DT as well. kirkwood-ts219.dtsi has
>
> i2c@11000 {
> status = "okay";
> clock-frequency = <400000>;
Ok, I did convert the i2c definition to use the devicetree.
The adt7476 device itself is not at reach of device tree,
AFAIK and requires more work at there?
Thanks for your valuable comments. Following is a new patch that
should address the problems and mistakes you pointed and also
some of the pointed by Jason Cooper. The nand and i2c are now
defined at DT and I also removed the pointless defines and
ARM_APPENDED_DTB. It is based against the Linus' official
3.6 version.
Best regards,
Tero
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This is a new kirkwood box made by Universal Scientific Industrial, Inc.
The product description is here:
http://www.usish.com/english/products_topkick1281p2.php
It is very similar to the dreamplug and other plug devices, with the
exception that it has room for a 2.5" SATA HDD internally.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Remove board specific gpio-fan driver registration. Moved into device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds DT board setup for the LaCie NAS Network Space Mini v2
(aka SafeBox). The hardware characteristics are very close to those of
the Network Space Lite v2. The main difference are:
- A GPIO fan which is only available on the NS2 Mini.
- A single USB host port is wired on the NS2 Mini. The NS2 Lite provides
an additional dual-mode USB port (host/device).
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds DT board setup for the LaCie NAS Network Space Lite v2.
This board is derived from the Network Space v2 and a lot of hardware
characteristics are shared.
- CPU: Marvell 88F6192 800Mhz
- SDRAM memory: 128MB DDR2 200Mhz
- 1 SATA port: internal
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- i2c EEPROM: 512 bytes (24C04 type)
- 2 USB2 ports: host and host/device
- 1 push button
- 1 SATA LED (bi-color, blue and red)
Note that the SATA LED is not compatible with the driver leds-ns2. The
LED behaviour ("on", "off" or "SATA activity blink") is controlled via
a single MPP (21).
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds DT board setup for LaCie Network Space v2 and parents,
based on the Marvell Kirkwood 6281 SoC. This includes Network Space v2
(Max) and Internet Space v2.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
mv64xxx_of_config requires that the tclk frequency be found
through the clk stuff rather than through device tree, so add
another override for the 2nd controller.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The kirkwood_pcie_scan_bus function duplicates the common code in
bios32.c, passing ops in will use the common code..
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
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Merge tag 'marvell-hwiocc-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Add hardware I/O coherency support for Armada 370/XP
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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Merge tag 'marvell-armadaxp-smp-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
From Michal Simek:
This branch depends on arm-soc devel/debug_ll_init branch because
we needed Rob's "ARM: implement debug_ll_io_init()"
(sha1: afaee03511ba8002b26a9c6b1fe7d6baf33eac86)
patch.
This branch also depends on zynq/dt branch because of previous major
zynq changes.
zynq/cleanup branch is subset of zynq/dt.
* 'zynq/multiplatform' of git://git.monstr.eu/linux-2.6-microblaze:
ARM: zynq: Remove all unused mach headers
ARM: zynq: add support for ARCH_MULTIPLATFORM
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: remove TTC early mapping
ARM: zynq: add clk binding support to the ttc
ARM: zynq: use zynq clk bindings
clk: Add support for fundamental zynq clks
ARM: zynq: dts: split up device tree
ARM: zynq: Allow UART1 to be used as DEBUG_LL console.
ARM: zynq: dts: add description of the second uart
ARM: zynq: move arm-specific sys_timer out of ttc
zynq: move static peripheral mappings
zynq: remove use of CLKDEV_LOOKUP
zynq: use pl310 device tree bindings
zynq: use GIC device tree bindings
Add/add conflict in arch/arm/Kconfig.debug.
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.
As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.
* 'next/dt-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (32 commits)
ARM: EXYNOS: DT Support for SATA and SATA PHY
ARM: dts: Remove broken-voltage property from sdhci node for exynos4210-trats
ARM: dts: Add node for touchscreen for exynos4210-trats
ARM: dts: Add node for touchscreen voltage regulator for exynos4210-trats
ARM: dts: Add node for i2c3 bus for exynos4210-trats
ARM: dts: Add nodes for GPIO keys available on Trats
ARM: dts: Update for pinctrl-samsung driver for exynos4210-trats
ARM: dts: Add nodes for pin controllers for exynos4x12
pinctrl: samsung: Add support for EXYNOS4X12
gpio: samsung: Skip registration if pinctrl driver is present on EXYNOS4X12
ARM: EXYNOS: Skip wakeup-int setup if pinctrl driver is used on EXYNOS4X12
ARM: dts: add board dts file for EXYNOS4412 based SMDK board
ARM: dts: Add support for EXYNOS4X12 SoCs
ARM: EXYNOS: Add devicetree node for TMU driver for exynos5
ARM: EXYNOS: Add devicetree node for TMU driver for exynos4
ARM: EXYNOS: Add MFC device tree support
ARM: dts: Enable serial controllers on Origen and SMDKV310
Documentation: Update samsung-pinctrl device tree bindings documentation
pinctrl: samsung: Add GPIO to IRQ translation
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
...
Add/add conflicts in:
arch/arm/boot/dts/exynos5250-smdk5250.dts
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/mach-exynos/mach-exynos5-dt.c
Signed-off-by: Olof Johansson <olof@lixom.net>
The ARM IM-PD1 add-on module has a few clock of its own, let's
move also these down to the drivers/clk/versatile driver dir
and get rid of any remaining oldschool Integrator clocks.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
From Maxime Ripard:
Here is a pull request to add the support for Allwinner A10 SoCs.
* sunxi/soc2:
ARM: sunxi: Add sunxi restart function via onchip watchdog
ARM: sunxi: Add sun4i and cubieboard support
ARM: sunxi: Add earlyprintk support for UART0 (sun4i)
ARM: sunxi: Restructure sunxi dts/dtsi files
Signed-off-by: Olof Johansson <olof@lixom.net>
- The code relies on rc_pci_fixup being called, which only happens
when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
this causes a booting failure with a non-obvious cause.
- Update rc_pci_fixup to set the class properly, copying the
more modern style from other places
- Correct the rc_pci_fixup comment
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
PMU interrupts start at IRQ_DOVE_PMU_START, not IRQ_DOVE_PMU_START + 1.
Fix the condition. (It may have been less likely to occur had the code
been written "if (irq >= IRQ_DOVE_PMU_START" which imho is the easier
to understand notation, and matches the normal way of thinking about
these things.)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: stable@vger.kernel.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
From Kukjin Kim:
Here is Samsung boards update for v3.8 and most of them are updates
for S3C64XX Cragganmore board.
* 'next/board-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Add missing device selects for Cragganmore
ARM: EXYNOS: Add missing USB regulators for origen
ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
ARM: S3C64XX: Add handset module to probed Glenfarclas modules
ARM: S3C64XX: Add WM2200 module for Cragganmore
ARM: S3C64XX: Add hookup for Deanston module on Cragganmore
ARM: S3C64XX: Handle new Amrut modules on Cragganmore
ARM: S3C64XX: Handle revision-specific differences in Cragganmore modules
ARM: S3C64XX: Provide platform data for Tomatin/Balblair on Cragganmore
ARM: S3C64XX: Update hookup for Arizona class devices
ARM: S3C64XX: Add more Glenfarclas module ID strings
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix the acknowledgement of PMU interrupts on Dove: some Dove hardware
has not been sensibly designed so that interrupts can be handled in a
race free manner. The PMU is one such instance.
The pending (aka 'cause') register is a bunch of RW bits, meaning that
these bits can be both cleared and set by software (confirmed on the
Armada-510 on the cubox.)
Hardware sets the appropriate bit when an interrupt is asserted, and
software is required to clear the bits which are to be processed. If
we write ~(1 << bit), then we end up asserting every other interrupt
except the one we're processing. So, we need to do a read-modify-write
cycle to clear the asserted bit.
However, any interrupts which occur in the middle of this cycle will
also be written back as zero, which will also clear the new interrupts.
The upshot of this is: there is _no_ way to safely clear down interrupts
in this register (and other similarly behaving interrupt pending
registers on this device.) The patch below at least stops us creating
new interrupts.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: stable@vger.kernel.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
From Kukjin Kim:
This includes supporting legacy i2c controller and ARM down clock
support for exynos5 and small changes.
[olof: It contains a dependency on samsung/hdmi for HDMI DT bindings, for some reason.]
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Clock settings for SATA and SATA PHY
ARM: EXYNOS: Add ARM down clock support
ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
ARM: EXYNOS: Add aliases for i2c controller
ARM: EXYNOS: Setup legacy i2c controller interrupts
ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms
ARM: EXYNOS: add clocks for exynos5 hdmi
ARM: dts: add device tree support for exynos5 hdmiddc
ARM: dts: add device tree support for exynos5 hdmiphy
ARM: dts: add device tree support for exynos5 mixer
ARM: dts: add device tree support for exynos5 hdmi
ARM: EXYNOS: Add dp clock support for EXYNOS5
ARM: SAMSUNG: call clk_get_rate for debugfs rate files
ARM: SAMSUNG: add clock_tree debugfs file in clock
Signed-off-by: Olof Johansson <olof@lixom.net>
cm-t3517 starting from revision 1.2 does not have the 32K oscilator
wired to the AM3517 SoC.
Therefore switch to use the GPTIMER for system clock.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.
As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.
* samsung/pinctrl:
pinctrl: samsung: Update error check for unsigned variables
pinctrl: samsung: Add support for EXYNOS4X12
Documentation: Update samsung-pinctrl device tree bindings documentation
pinctrl: samsung: Add GPIO to IRQ translation
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
pinctrl: samsung: Use one GPIO chip per pin bank
pinctrl: exynos: Use one IRQ domain per pin bank
pinctrl: samsung: Include bank-specific eint offset in bank struct
pinctrl: samsung: Hold pointer to driver data in bank struct
pinctrl: samsung: Match pin banks with their device nodes
ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
pinctrl: samsung: Distinguish between pin group and bank nodes
pinctrl: samsung: Remove static pin enumerations
pinctrl: samsung: Assing pin numbers dynamically
pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
pinctrl: samsung: Detect and handle unsupported configuration types
CONFIG_OMAP_32K_TIMER is kind of standing on the single zImage way.
Make OMAP2+ timer code independant from the CONFIG_OMAP_32K_TIMER
setting.
To remove the dependancy, several conversions/additions had to be done:
1) Timer initialization functions are named by the platform
name and the clock source in use.
This also makes it possible to define and use the GPTIMER as the
clock source instead of the 32K timer on platforms that do not have
the 32K timer ip block or the 32K timer is not wired on the board.
Currently, the the timer is chosen in the machine_desc structure on
per board basis. Later, DT should be used to choose the timer.
2) Settings under the CONFIG_OMAP_32K_TIMER option are used as defaults
and those under !CONFIG_OMAP_32K_TIMER are removed.
This removes the CONFIG_OMAP_32K_TIMER on OMAP2+ timer code.
3) Since we have all the timers defined inside machine_desc structure
and we no longer need the fallback to gp_timer clock source in case
32k_timer clock source is unavailable (namely on AM33xx), we no
longer need the #ifdef around omap2_sync32k_clocksource_init()
function. Remove the #ifdef CONFIG_OMAP_32K_TIMER around the
omap2_sync32k_clocksource_init() function.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Jon Hunter <jon-hunter@ti.com>
From Kukjin Kim:
This is for Samsung gpio stuff and got the ack from Linus Walleij.
* 'next/gpio-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
gpio: samsung: use pr_* instead of printk
gpio: samsung: Fix input mode setting function for GPIO int
ARM: SAMSUNG: Insert bitmap_gpio_int member in samsung_gpio_chip
From Kukjin Kim:
This is for adding support for DT based exynos5250 hdmi and it adds
device node for hdmi, mixer, hdmiphy and hdmiddc.
* 'next/hdmi-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms
ARM: EXYNOS: add clocks for exynos5 hdmi
ARM: dts: add device tree support for exynos5 hdmiddc
ARM: dts: add device tree support for exynos5 hdmiphy
ARM: dts: add device tree support for exynos5 mixer
ARM: dts: add device tree support for exynos5 hdmi
From Kukjin Kim:
* 'next/cleanup-samsung-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: use devm_ functions for ADC driver
ARM: EXYNOS: no duplicate mask/unmask in eint0_15
ARM: S3C24XX: SPI clock channel setup is fixed for S3C2443
ARM: EXYNOS: Remove i2c0 resource information and setting of device names
ARM: S3C64XX: Statically define parent clock of "camera" clock
ARM: S3C64XX: Remove duplicated camera clock
ARM: EXYNOS: Add missing static storage class specifiers in clock-exynos5.c
ARM: EXYNOS: Make combiner_of_init function static
ARM: EXYNOS: Make s3c_device_i2c0 always use id 0
ARM: EXYNOS: Remove wrongly placed usb2.0 PHY_CFG definition from PMU_REG
ARM: EXYNOS: reorder inclusions of <linux/platform_data/xxx.h>
ARM: EXYNOS: Remove unused static uart resource information
ARM: EXYNOS: Remove static io-remapping for gic and combiner
ARM: EXYNOS: Remove wrong I2S0 clock from peril clock
ARM: EXYNOS: remove the MMC_CAP2_BROKEN_VOLTAGE
From Alexander Shiyan:
The main direction of this patchset - approaching the platform to the
possibility of using configurations with multiple platforms in a single
kernel. Added support of the majority of the necessary kernel symbol.
Also part of the driver code used only for the platform was moved to the
board code and converted to the use of standard drivers.
* clps711x/soc2:
MAINTAINERS: Add ARM CLPS711X entry
ARM: clps711x: Update defconfig due latest changes and new kernel symbols
ARM: clps711x: Rename board files to match functionality
ARM: clps711x: edb7211: Add support for NOR-Flash
ARM: clps711x: Moving backlight controls of framebuffer driver to the board
ARM: clps711x: p720t: Special driver for handling NAND memory is removed
ARM: clps711x: Moving power management of framebuffer driver to the board
ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed
ARM: clps711x: Unused empty "ACK" calls for IRQ-chips removed
ARM: clps711x: Add FIQ interrupt handling
ARM: clps711x: Implement usage "MULTI_IRQ_HANDLER" kernel option for a platform
ARM: clps711x: Implement usage "SPARSE_IRQ" kernel option for a platform
ARM: clps711x: cdb89712: Special driver for handling memory is removed
ARM: clps711x: Always select AUTO_ZRELADDR for a platform
ARM: clps711x: p720t: Unneeded inclusion of head-sa1100.S removed
ARM: clps711x: Transform clps711x-framebuffer to platform driver and use it
ARM: clps711x: p720t: Using "leds-gpio" driver for LED control
ARM: clps711x: Using platform_driver for ethernet device
This patch moves the backlight controls for clps711x-framebuffer driver
to the board code. To control we use "generic-bl" driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
[olof: fixed space/tab whitespace in drivers/video/clps711xfb.c]
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch provide migration to using "gpio-nand" driver instead of using
special driver for handling NAND memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch moves the power management for clps711x-framebuffer driver
to the board code. To control we use "platform-lcd" driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch provide migration to using "gpio-nand" and "basic-mmio-gpio"
drivers instead of using special driver for handling NAND memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
CLPS711X-target CPU can have a several FIQ interrupts. With this patch
we adds handling for a one which will be used for ALSA PCM later.
Since FIQ have a separate handler we only add "mask" and "unmask" calls
which will used for enable/disable_irq functions.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch provide migration to using "physmap-flash" and "mtd-ram"
drivers instead of using special driver for handling memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is required for some of the clps711x series, so we're bringing in
the dependency explicitly.
By Linus Walleij (5) and others
via Linus Walleij
* depends/gpio-devel:
GPIO: clps711x: use platform_device_unregister in gpio_clps711x_init()
gpio/tc3589x: convert to use the simple irqdomain
gpio/em: convert to linear IRQ domain
gpio/mvebu: convert to use irq_domain_add_simple()
gpio/tegra: convert to use linear irqdomain
gpiolib: unlock on error in gpio_export()
gpiolib: add gpio get direction callback support
GPIO: clps711x: Fix direction logic for PORTD
GPIO: clps711x: Fix return value for gpio_clps711x_get
gpiolib: Refactor gpio_export
GPIO: vt8500: Add extended gpio bank for WM8505/WM8650
gpio: clps711x: delete local <mach/gpio.h> header
GPIO: Add support for GPIO on CLPS711X-target platform
DA9055 GPIO driver
gpio/gpio-omap: Use existing pointer to struct device
gpio/gpio-pl061: Covert to use devm_* functions
Signed-off-by: Olof Johansson <olof@lixom.net>
Armada 370 and XP come with an unit called coherency fabric. This unit
allows to use the Armada 370/XP as a nearly coherent architecture. The
coherency mechanism uses snoop filters to ensure the coherency between
caches, DRAM and devices. This mechanism needs a synchronization
barrier which guarantees that all the memory writes initiated by the
devices have reached their target and do not reside in intermediate
write buffers. That's why the architecture is not totally coherent and
we need to provide our own functions for some DMA operations.
Beside the use of the coherency fabric, the device units will have to
set the attribute flag of the decoding address window to select the
accurate coherency process for the memory transaction. This is done
each device driver programs the DRAM address windows. The value of the
attribute set by the driver is retrieved through the
orion_addr_map_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Recent SoC such as Armada 370/XP came with the possibility to deal
with the I/O coherency by hardware. In this case the transaction
attribute of the window must be flagged as "Shared transaction". Once
this flag is set, then the transactions will be forced to be sent
through the coherency block, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Expose another DMA operations function: arm_dma_set_mask. This
function will be added to a custom DMA ops for Armada 370/XP.
Depending of its configuration Armada 370/XP can be set as a "nearly"
coherent architecture. In this case the DMA ops is made of:
- specific functions for this architecture
- already exposed arm DMA related functions
- the arm_dma_set_mask which was not exposed yet.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
This enables SMP support on the Armada XP processor. It adds the
mandatory functions to support SMP such as: the SMP initialization
functions in platsmp.c, the secondary CPU entry point in headsmp.S and
the CPU hotplug initial support in hotplug.c.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
PJ4B is an implementation of the ARMv7 (such as the Cortex A9 for
example) released by Marvell. This CPU is currently found in
Armada 370 and Armada XP SoCs. This patch provides a support for the
specific initialization of this CPU.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
This patch enhances the IRQ controller driver to add support for
Inter-Processor-Interrupts that are needed to enable SMP support.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and Armada XP SOCs have a power management service unit
which is responsible for powering down and waking up CPUs and other
SOC units. This patch adds support for this unit.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and Armada XP SOCs have a coherency fabric unit which
is responsible for ensuring hardware coherency between all CPUs and
between CPUs and I/O masters. This patch provides the basic support
needed for SMP.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
This patch modifies pin control groups of SD pins on EXYNOS4210
and EXYNOS4X12 to use drive strength 3 as a default value which
corresponds to S5P_GPIO_DRVSTR_LV4 in legacy non-DT code.
This is needed at least on Origen board for sdhci2 to work and
if any other drive strength is required on each board, we can
overide it.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited commit message]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree nodes for power domains available
on EXYNOS4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a way to specify bindings between devices and power
domains using device tree.
A device can be bound to particular power domain by adding a
power-domain property containing a phandle to the domain. The device
will be bound to the domain before binding a driver to it and unbound
after unbinding a driver from it.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds initialization of name field in generic power domain
struct.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Initial state of power domains might vary on different boards and with
different bootloaders.
This patch adds detection of initial state of power domains when being
registered from DT.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds fixed voltage vmmc regulator to dts file of Origen
board.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch modifies sdhci nodes present in Origen device tree source
to use current generic mmc bindings.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch updates all parts of Origen dts related to pin configuration
to use new GPIO and pinctrl bindings, instead of (now unsupported on
Exynos4) legacy gpio-samsung bindings.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch changes memory configuration defined in dts file of Origen
board from single 1 GiB section into four 256 MiB sections to match
section size limit.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Needed to match device ids for clocks, etc.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is similar to a recent commit for exynos5250 titled:
ARM: EXYNOS: Add aliases for i2c controller
Adding aliases will be useful to prevent warnings in a future
change. See:
i2c: s3c2410: Get the i2c bus number from alias id
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
chan->end is tested for being NULL. However in the event that it is NULL, the
subsequent assignment statement would lead to NULL pointer dereference.
Thus dereferencing it only when it is not NULL.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Rob Herring:
Use common debug_ll_init function and remove the static mapping code
from mach-highbank.
* tag 'highbank-debugll-cleanup' of git://sources.calxeda.com/kernel/linux:
ARM: highbank: use common debug_ll_io_init
ARM: implement debug_ll_io_init()
From Pawel Moll:
* 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux:
ARM: vexpress: Remove motherboard dependencies in the DTS files
ARM: vexpress: Start using new Versatile Express infrastructure
ARM: vexpress: Add config bus components and clocks to DTs
mfd: Versatile Express system registers driver
mfd: Versatile Express config infrastructure
From Mike Turquette:
* depends/clk:
clk: Common clocks implementation for Versatile Express
clk: Versatile Express clock generators ("osc") driver
CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clock
clk: fix return value check in sirfsoc_of_clk_init()
clk: fix return value check in of_fixed_clk_setup()
clk: ux500: Update sdmmc clock to 100MHz for u8500
clk: ux500: Support prcmu ape opp voltage clock
mfd: dbx500: Export prmcu_request_ape_opp_100_voltage
clk: Don't return negative numbers for unsigned values with !clk
clk: Fix documentation typos
clk: Document .is_enabled op
clk: SPEAr: Vco-pll: Fix compilation warning
From Stephen Warren:
ARM: bcm2835: defconfig updates
procfs and sysfs are enabled in bcm2835_defconfig.
* tag 'bcm2835-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: enable procfs and sysfs in defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
From Stephen Warren:
ARM: bcm2835: core SoC enhancements
A machine restart/reboot implementation is added. The GPIO/pinmux
controller is instantiated, and dummy gpio.h added.
* tag 'bcm2835-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: enable GPIO/pinctrl
ARM: bcm2835: implement machine restart hook
Signed-off-by: Olof Johansson <olof@lixom.net>
From Stephen Warren:
ARM: tegra: defconfig update
Many new features are enabled in tegra_defconfig:
* BRCMFMAC: wlan driver, enable as module.
* MTD, MTD_CHAR, MTD_M25P80, SPI_TEGRA20_SLINK, CONFIG_SPI_TEGRA20_SFLASH
to enable serial flash on Cardhu and TrimSlice.
* PWM/backlight features for use with tegradrm.
* tegradrm; Tegra's new display driver.
* CMA, so that tegradrm can allocate large buffers.
* SquashFS, which is used as the root filesystem on boards based on
the Tamonten processor module.
* tag 'tegra-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: defconfig updates
From Stephen Warren:
ARM: tegra: cpuidle enhancements
A cpuidle state "LP2" is added, which power-gates the CPUs. Support for
CPUs 1..n is essentially complete, although support for CPU0 could
benefit from future use of coupled-cpuidle or similar techniques.
A couple of very minor cleanups to cpuidle were included too.
This pull request is based on tegra-for-3.8-soc.
* tag 'tegra-for-3.8-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: retain L2 content over CPU suspend/resume
ARM: tegra30: cpuidle: add powered-down state for CPU0
ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function
ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops
ARM: tegra30: common: enable csite clock
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
ARM: tegra: cpuidle: add CPU resume function
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX"
ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATE
From Stephen Warren:
ARM: tegra: core SoC code enhancements
Various small clock initialization table and driver changes to support
WiFi modules, SPI controllers, and host1x (graphics/display hardware).
Various AHB/APB-related clocks were added to the Tegra30 clock driver.
The level 2 cache initialization is now driven by data from device tree,
and the cache configuration tweaked.
AUXDATA is added to support SPI controllers and host1x.
Code to decode Tegra's "speedo" process identification fuses is added.
This pull request is based on tegra-for-3.8-cleanup.
* tag 'tegra-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (26 commits)
ARM: tegra: Add Tegra30 host1x clock support
ARM: tegra: Add AUXDATA for Tegra30 host1x
ARM: tegra: Add Tegra20 host1x clock support
ARM: tegra: Add AUXDATA for Tegra20 host1x
ARM: tegra: Tegra30 speedo-based process identification
ARM: tegra: Add speedo-based process identification
ARM: tegra: flexible spare fuse read function
ARM: tegra: Implement 6395/1 for Tegra
ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt
ARM: tegra: enable data prefetch on L2
ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt
ARM: tegra: common: using OF api for L2 cache init
ARM: tegra: dt: add L2 cache controller
ARM: tegra30: clocks: add AHB and APB clocks
ARM: tegra: set up wlan clocks for tegra dt
ARM: tegra: move irammap.h to mach-tegra
ARM: tegra: move iomap.h to mach-tegra
ARM: tegra: remove <mach/dma.h>
ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/
ARM: tegra: remove unnecessary includes of <mach/*.h>
...
Remove empty unused mach/hardware.h.
mach/irqs.h is unused because SPARSE_IRQ are ON by default.
mach/timex.h is unused because of CONFIG_ARCH_MULTIPLATFORM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
The majority of changes are necessary to remove dependencies on header
files within arch/arm/mach-zynq/include/mach:
uncompress.h
- Deleted. It is unused for ARCH_MULTIPLATFORM builds.
uart.h:
- Move uart definitions out of uart.h into debug/zynq.S, which is
now the only user
zynq_soc.h:
- Move SCU address definitions into common.c.
- Other #defines, such as PERIPHERAL_CLOCK_RATE, TTC0_BASE, etc, are
unused and can be dropped
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Convert low-level debugging routines to make use of debug_ll_io_init().
This is part of the preparation for ARCH_MULTIPLATFORM support for Zynq.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Now that the TTC driver has proper support for DT bindings, it is not
necessary for the registers to be mapped early. They will be mapped
during clock initialization using of_iomap(). Remove the early mapping.
In addition, remove the extraneous zynq_soc.h include from the timer
driver.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
From Lee Jones. It's an update of the previous ux500/dt branch with a few more
patches:
* 'ste-dt-for-next' of git://git.linaro.org/people/ljones/linux-3.0-ux500:
ARM: ux500: Describe UART platform registering issues more accurately
ARM: ux500: Enable all MMC devices on the u9540 when booting with DT
ARM: ux500: Enable SDI4 port on the u9540 when booting with Device Tree
ARM: ux500: Add UART support to the u9540 Device Tree
ARM: ux500: Add skeleton DTS file for the u9540
ARM: ux500: Add SDI (MMC) support to the HREF Device Tree
ARM: ux500: Move regulator-name properties out to board DTS files
Signed-off-by: Olof Johansson <olof@lixom.net>
This time, only one patch: Adding the motor PWM to lpc32xx.dtsi
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Merge tag 'lpc32xx-dts-for-3.7' of git://git.antcom.de/linux-2.6 into next/dt
From Roland Stigge:
DTS updates for the LPC32xx Soc for 3.7
This time, only one patch: Adding the motor PWM to lpc32xx.dtsi
* tag 'lpc32xx-dts-for-3.7' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Add the motor PWM to base dts file
Signed-off-by: Olof Johansson <olof@lixom.net>
Just a few minor/trivial cleanups.
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Merge tag 'bcm2835-for-3.8-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/cleanup
From Stephen Warren:
ARM: bcm2835: cleanup
Just a few minor/trivial cleanups.
* tag 'bcm2835-for-3.8-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: remove useless variables from Makefile.boot
ARM: bcm2835: Fix typo in the error message
ARM: bcm2835: Add missing static modifiers
Various cleanups and enhancements are made to core Tegra code towards the
aim of including Tegra in a multi-platform ARM kernel:
RTC, timer, and TWD are configured via device tree.
SPARSE_IRQ is enabled.
Tegra's debug_ll options are simplified, and the macros brought into
line with other multi-platform implementations, and moved to the new
common location.
Two headers still need to be eliminated in order to include Tegra in a
multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs
to be invented to replace parts of clk.h. powergate.h might be replaced
by regulators; this needs more investigation.
This pull request is based on tegra-for-3.8-dt, followed by a merge of
arm-soc's devel/debug_ll_init branch.
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Merge tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform
From Stephen Warren:
ARM: tegra: single-zImage preparation work
Various cleanups and enhancements are made to core Tegra code towards the
aim of including Tegra in a multi-platform ARM kernel:
RTC, timer, and TWD are configured via device tree.
SPARSE_IRQ is enabled.
Tegra's debug_ll options are simplified, and the macros brought into
line with other multi-platform implementations, and moved to the new
common location.
Two headers still need to be eliminated in order to include Tegra in a
multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs
to be invented to replace parts of clk.h. powergate.h might be replaced
by regulators; this needs more investigation.
This pull request is based on tegra-for-3.8-dt, followed by a merge of
arm-soc's devel/debug_ll_init branch.
* tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (58 commits)
ARM: tegra: move debug-macro.S to include/debug
ARM: tegra: don't include iomap.h from debug-macro.S
ARM: tegra: decouple uncompress.h and debug-macro.S
ARM: tegra: simplify DEBUG_LL UART selection options
ARM: tegra: select SPARSE_IRQ
ARM: tegra: enhance timer.c to get IO address from device tree
ARM: tegra: enhance timer.c to get IRQ info from device tree
ARM: timer: fix checkpatch warnings
ARM: tegra: add TWD to device tree
ARM: tegra: define DT bindings for and instantiate RTC
ARM: tegra: define DT bindings for and instantiate timer
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
...
A wide variety of device tree additions are made across many Tegra
boards:
* WiFi is supported on Seaboard, Ventana, and Cardhu.
* An I2C mux is added for Ventana, and Tamonten.
* SPI flash is added to Cardhu, and TrimSlice.
* Temperature sensors are added to Harmony, Tamonten, and Ventana.
* host1x (graphics/display controller) is added to the SoC include files.
* HDMI displays are enabled on Harmony, TrimSlice, Tamonten, Plutux, Tec,
and Whistler.
This pull request is based on tegra-for-3.8-soc.
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Merge tag 'tegra-for-3.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren:
ARM: tegra: device tree changes
A wide variety of device tree additions are made across many Tegra
boards:
* WiFi is supported on Seaboard, Ventana, and Cardhu.
* An I2C mux is added for Ventana, and Tamonten.
* SPI flash is added to Cardhu, and TrimSlice.
* Temperature sensors are added to Harmony, Tamonten, and Ventana.
* host1x (graphics/display controller) is added to the SoC include files.
* HDMI displays are enabled on Harmony, TrimSlice, Tamonten, Plutux, Tec,
and Whistler.
This pull request is based on tegra-for-3.8-soc.
* tag 'tegra-for-3.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (47 commits)
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
ARM: tegra: dts: add sflash controller dt entry
ARM: tegra: ventana: Add NCT1008 temperature sensor
ARM: tegra: tamonten: Add NCT1008 temperature sensor
ARM: tegra: harmony: Add ADT7641 temperature sensor
ARM: tegra: tec: Remove redundant DT properties
ARM: tegra: tamonten: Add DDC/PTA pinmux
ARM: tegra: dts: cardhu: enable SLINK4
ARM: tegra: dts: add slink controller dt entry
ARM: dt: tegra: ventana: define pinmux for ddc
ARM: dt: t30 cardhu: set pinmux and power for wlan
ARM: dt: t20 ventana: set pinmux and power for wlan
...
Various trivial cleanup changes of the Tegra code for 3.8.
Many of the changes simply remove useless #include statements, which
enable those headers to be removed or moved later, as work towards
multi-platform zImage support.
<mach/{iram,io}map.h> are moved up to arch/arm/mach-tegra to prevent
any new code outside mach-tegra from using them.
Finally, the regulator definitions in all board device tree files are
updated to use the new simpler syntax that was agreed upon.
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Merge tag 'tegra-for-3.8-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup
From Stephen Warren:
ARM: tegra: cleanup for 3.8
Various trivial cleanup changes of the Tegra code for 3.8.
Many of the changes simply remove useless #include statements, which
enable those headers to be removed or moved later, as work towards
multi-platform zImage support.
<mach/{iram,io}map.h> are moved up to arch/arm/mach-tegra to prevent
any new code outside mach-tegra from using them.
Finally, the regulator definitions in all board device tree files are
updated to use the new simpler syntax that was agreed upon.
* tag 'tegra-for-3.8-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: move irammap.h to mach-tegra
ARM: tegra: move iomap.h to mach-tegra
ARM: tegra: remove <mach/dma.h>
ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/
ARM: tegra: remove unnecessary includes of <mach/*.h>
iommu: tegra: remove include of <mach/iomap.h>
staging: nvec: remove include of <mach/iomap.h>
crypto: tegra: remove include of <mach/clk.h>
ARM: tegra: update *.dts for regulator-compatible deprecation
usb: phy: tegra remove include of <mach/iomap.h>
usb: host: tegra remove include of <mach/iomap.h>
Let's stop spawning the pinctrl driver from the GPIO driver,
we have these two mechanisms broken apart now, and they can
each probe in isolation. If the GPIO driver cannot find its
pin controller (pinctrl-u300), the pin controller core will
tell it to defer probing.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- conversion of watchdog to DT
- usart definition for evk-pro3 board
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Merge tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
More DT material for AT91:
- conversion of watchdog to DT
- usart definition for evk-pro3 board
* tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dts: evk-pro3: enable watchdog
ARM: at91/dts: add at91sam9_wdt driver to at91sam926x, at91sam9g45
watchdog: at91sam9_wdt: add device tree support
ARM: at91: dt: evk-pro3: enable uart0 and uart2
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Merge tag 'at91-header' of git://github.com/at91linux/linux-at91 into next/headers
From Nicolas Ferre:
One fix related to UART for the "headers move" branch
* tag 'at91-header' of git://github.com/at91linux/linux-at91:
atmel: move ATMEL_MAX_UART to platform_data/atmel.h
clps711x-framebuffer driver needs to be updated and this is a first step
to make driver better. With this patch we are convert clps711x-framebuffer
to platform device and load this driver from board code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
Instead of manually create LED class device, we will use "leds-gpio"
driver for LED control.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch removes static mappings for ethernet devices. Now we will use
platform_driver for ethernet devices.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux into next/soc
From Maxime Ripard:
Allwinner SoC support for 3.8
* tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux:
ARM: sunxi: Add entry to MAINTAINERS
ARM: sunxi: Add device tree for the A13 and the Olinuxino board
ARM: sunxi: Add earlyprintk support
ARM: sunxi: Add basic support for Allwinner A1x SoCs
irqchip: sunxi: Add irq controller driver
clocksource: sunxi: Add Allwinner A1X Timer Driver
clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
* Since 3.3 gpio wakeup is broken on pxa25x (tested on corgi and poodle).
* Use gpio_set_wake like done for pxa27x with commit id
* b95ace54a2
Signed-off-by: Andrea Adami <andrea.adami@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
A couple devices' DT compatible values only contained the device name
without any vendor prefix. Add the missing vendor prefixes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This dts file is based on the Snow dts file in the Chromium OS kernel
tree with the following changes:
* Some details have been updated to match the exynos5250-smdk5250.dts
file from linux-next (as of c11068538994430547722dc9fb515a0ceefd5cb9).
* This file doesn't include references to hardware whose upstream
support isn't quite there yet. That includes most i2c devices.
Note that most i2c busses have been included with no devices.
The Snow dts file is mostly just an include of the "cros5250" dts file
which describes a class of similar boards. Support for other boards has
not yet been send upstream.
With this file and a change to use UART3 for serial output I can:
* Boot to a command line using either SD or EMMC as a root filesystem
* See the power button and lid switch using evtest.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The aliases for dwmmc were placed in the SMDK5250 dts file but really
should be common for all exynos5250 boards. Move it to the common CPU
file.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Merge tag 'marvell-boards-net-for-3.8' of github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell boards changes related to Ethernet, for 3.8
Conflicts:
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-xp-db.dts
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The mvneta driver for the Marvell Armada 370/XP Ethernet devices has
gained proper clock framework integration, and the corresponding
Device Tree nodes now have a correct 'clocks' pointer.
The 'clock-frequency' properties in the various .dts files for Armada
370/XP boards have therefore become useless.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The mvneta driver now understands a standard 'clocks' clock pointer
property in the Device Tree nodes for the Ethernet devices, so we add
the right clock reference for the different Ethernet ports of the
Armada 370/XP SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Move iommu/iovmm headers from plat/ to platform_data/ as part of the
single zImage work.
Partially based on an earlier version by Ido Yariv <ido@wizery.com>.
Cc: Ido Yariv <ido@wizery.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This file should not be in arch/arm. Move it to drivers/iommu
to allow making most of the header local to drivers/iommu.
This is needed as we are removing plat and mach includes
from drivers for ARM common zImage support.
Cc: Ido Yariv <ido@wizery.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab@infradead.org>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Cc: linux-media@vger.kernel.org
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks like the iommu framework does not have generic functions
exported for all the needs yet. The hardware specific functions
are defined in files like intel-iommu.h and amd-iommu.h. Follow
the same standard for omap-iommu.h.
This is needed because we are removing plat and mach includes
for ARM common zImage support. Further work should continue
in the iommu framework context as only pure platform data will
be communicated from arch/arm/*omap*/* code to the iommu
framework.
Cc: Ido Yariv <ido@wizery.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Cc: linux-media@vger.kernel.org
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The iopgtable header file is only used by the iommu & iovmm drivers, so
move it to drivers/iommu/, as part of the single zImage effort.
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab@infradead.org>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Signed-off-by: Ido Yariv <ido@wizery.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
[tony@atomide.com: updated to be earlier in the series]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since iommu is not supported on OMAP1 and will not likely to ever be
supported, merge plat/iommu2.h into iommu.h so only one file would have
to move to platform_data/ as part of the single zImage effort.
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab@infradead.org>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Signed-off-by: Ido Yariv <ido@wizery.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
UARTs no longer require call-back information, since the reset
call-back was removed in 43b5f0d692.
The only AUXDATA dependencies remaining for UARTs are DMA settings.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The u9540 supports 3 MMC devices. This patch enables two of them
and updates the configuration of the already enabled SDI4 port.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Here we add the device node for the SDI4 (MMC) port to the u9540
Device Tree source file. This will allow successful probing of
the internal MMC storage device when booting with DT enabled.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Add the 3 UART nodes required to enable serial ports on the u9540.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This patch sees the creation of a sparse Device Tree file for
ST-Ericsson's latest development board supporting the latest
dual-core Cortex-a9 u9540 SoC.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Here we add the Device Tree nodes which are required to successfully
probe the MMCI driver which will enable the four cards available on
ST-Ericsson's HREF hardware development platform.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Regulator supply names should be allocated by board rather than
per SoC, as the same SoC could be wired differently on varying
hardware. Here we push all regulator-name allocation out to the
dbx5x0 subordinate board files; HREF and Snowball.
Requested-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
With DT support for Marvell XOR DMA engine, make use of it on Dove.
Also remove the now redundant code in DT board init for xor engines.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Use DT to describe the two XOR DMA engines on Kirkwood. Remove the
C code initialization.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The pool_size is always PAGE_SIZE, and since it is a software
configuration paramter (and not a hardware description parameter), we
cannot make it part of the Device Tree binding, so we'd better remove
it from the platform_data as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
There is no need for the platform_data to give this ID, it is simply
the channel number, so we can compute it inside the driver when
registering the channels.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Since we got rid of the per-XOR channel 'mv_xor' driver, now the
per-XOR engine driver that used to be called 'mv_xor_shared' can
simply be named 'mv_xor'.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
'struct mv_xor_shared_platform_data' used to be the platform_data
structure for the 'mv_xor_shared', but this driver is going to be
renamed simply 'mv_xor', so also rename its platform_data structure
accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
mv_xor_platform_data used to be the platform_data structure associated
to the 'mv_xor' driver. This driver no longer exists, and this data
structure really contains the properties of each XOR channel part of a
given XOR engine. Therefore 'struct mv_xor_channel_data' is a more
appropriate name.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Now that xor0 and xor1 are registered in a single driver manner, the
orion_xor_init_channels() function has become useless.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Instead of registering one 'mv_xor_shared' device for the XOR engine,
and then two 'mv_xor' devices for the XOR channels, pass the channels
properties as platform_data for the main 'mv_xor_shared' device.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Instead of registering one 'mv_xor_shared' device for the XOR engine,
and then two 'mv_xor' devices for the XOR channels, pass the channels
properties as platform_data for the main 'mv_xor_shared' device.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Add the SATA device tree bindings for
- Armada XP evaluation board (DB-78460-BP)
- Armada 370 evaluation board (DB-88F6710-BP-DDR3)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
For Armada 370/XP we have the same problem that for the commit
cb01b63, so we applied the same solution: "The default 256 KiB
coherent pool may be too small for some of the Kirkwood devices, so
increase it to make sure that devices will be able to allocate their
buffers with GFP_ATOMIC flag"
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
This patch adds support for the Cubieboard based on the Allwinner
A10/sun4i SoC. Currently only UART is supported. Other devices
will eventually follow.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
For the new sun4i/Cubieboard (A10) support, lets re-strucure the
sun5i dts files to make it more generic. Those are the new
dts/dtsi files:
sunxi.dtsi - Devices common to all Allwinner sunXi SoC's
sun4i.dtsi - sun4i Devices, will include sunxi.dtsi
sun5i.dtsi - sun5i Devices, will include sunxi.dtsi
board.dts - will include either sun4i.dtsi or sun5i.dtsi
Additionally the "duart" label in the olinuxino.dts is changed to
"uart1".
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
With true DT clock providers available switch Kirkwood clock setup in
DT- enabled boards. While AUXDATA can be removed completely from bus
probing, some devices still don't know about DT. Therefore, some clkdev
aliases are created until these devices also move to DT.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
With true DT clock providers available switch Dove clock setup in DT-
enabled boards. While AUXDATA can be removed completely from bus probing,
some devices still don't know about DT at all. Therefore, some clock
aliases are created until the devices also move to DT.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This patch adds Device Nodes for SATA and SATA PHY device.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
[kgene.kim@samsung.com: removed address definitions as per comments]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds neccessary clock entries for SATA, SATA PHY and
I2C_SATAPHY
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch uses devm_* functions for probe function in ADC driver.
It reduces code size and simplifies the code.
Signed-off-by: Eunki Kim <eunki_kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
chained_irq_enter/exit() already mask&ack/unmask the chained interrupt.
There is no need to also explicitly do it in the handler.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit 8214513 ("ARM: EXYNOS: fix address for EXYNOS4 MDMA1")
changed EXYNOS specific setup of PL330 DMA engine to use 'non-secure'
mdma1 address instead of 'secure' one (from 0x12840000 to 0x12850000)
to fix issue with some Exynos4212 SOCs. Unfortunately it brakes
PL330 setup for revision 0 of Exynos4210 SOC (mdma1 device cannot
be found at 'non-secure' address):
[ 0.566245] dma-pl330 dma-pl330.2: PERIPH_ID 0x0, PCELL_ID 0x0 !
[ 0.566278] dma-pl330: probe of dma-pl330.2 failed with error -22
Fix it by using 'secure' mdma1 address on Exynos4210 revision 0 SOC.
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In idle state down clocking the arm cores can result in power
savings. Program the power control registers to achieve this and
save these registers across a suspend/resume cycle.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The broken voltage property has been replaced with auto detection based
on voltages available on vmmc voltage regulator, so there is no use for
it now.
This patch removes the now unused property from Trats Device Tree
sources.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previously unnoticed due to selection by other machines.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Actually, SPI channel 0 on 2443 is mapped to HS SPI controller,
and to enable s3c2410-spi controller, we should power on channel
1 in PCLKCON. There is no channel 0 SPI on s3c2443, so delete its
clock.
Signed-off-by: Alexander Varnin <fenixk19@mail.ru>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On resuming from suspend the i2c configuration register that is part
of system controller resets to 0xf. This sets the interrupt source to
the new high speed i2c rather than the legacy one that we are using.
Save and restore the I2C_CFG register for exynos5 to fix this.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On Exynos5 we have a new high-speed i2c controller. The interrupt
sources for the legacy and new controller are muxed and are controlled
via the SYSCON I2C_CFG register. At reset the interrupt source is
configured for the high-speed controller, to continue using the old
i2c controller we need to modify the I2C_CFG register.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a device tree node for the Melfas MMS114-controlled
touchscreen present on Samsung Trats board.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree node for a fixed voltage regulator used for
touchscreen on Samsung Trats board.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree node for i2c3 bus to device tree source
of Samsung Trats board. This bus is used by mms114 touchscreen
controller, for which support will be added in separate patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch extends dts file of Samsung Trats board to add support for
available GPIO keys using gpio-keys driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch updates all parts of Trats dts related to pin configuration
to use new GPIO and pinctrl bindings, instead of (now unsupported on
Exynos4) legacy gpio-samsung bindings.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In order to start upstreaming Broadcom SoC support, create
a starting hierarchy, arch and dts files.
The first support SoC family that is planned is the
BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile
SoC cores.
This code is just the skeleton code for get the machine upstreamed. It
has been made MULTIPLATFORM compatible.
Next steps
----------
Upstream a basic set of drivers - sufficient for a console boot to
ramdisk. These will includer timer, gpio, i2c drivers.
After this basic set, we will proceed with a more comprehensive set
of drivers for the 281XX SoC family.
v2 patch mods
--------
- Remove l2x0_of_init call as there were problems with the code.
A separate patch will be submitted with cache init code
- Rename capri files and refs to bcm281xx-based names
- Add bcm281xx binding doc
- various misc cleanups
v3 patch mods
-------------
- Remove extra #include lines
- Remove remaining references to capri
- dt uart chipset string added
- cleaned up chip # references
v4 patch mods
-------------
- swap order of compatible definitions for uart
- fix typo
v5 patch mods
-------------
- Rename bcm281xx to bcm11351 in dts+code,
leaving references to bcm281xx only in help+comments.
v6 patch mods
-------------
- fix typo in uart 'compatible' string
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
of include file ordering in the EVM file.
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Merge tag 'davinci-for-v3.8/board' of git://gitorious.org/linux-davinci/linux-davinci into next/boards
From Sekhar Nori:
These changes add PRUSS support on DA850 EVM. There is also fixup
of include file ordering in the EVM file.
* tag 'davinci-for-v3.8/board' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da850 evm: register uio_pruss device
ARM: davinci: da850 evm: clean up include ordering
ARM: davinci: da8xx: add DA850 PRUSS support
ARM: davinci: add platform hook to fetch the SRAM pool
ARM: davinci: da850: changed SRAM allocator to shared ram.
ARM: davinci: sram: switch from iotable to ioremapped regions
uio: uio_pruss: replace private SRAM API with genalloc
ARM: davinci: serial: provide API to initialze UART clocks
ARM: davinci: convert platform code to use clk_prepare/clk_unprepare
Signed-off-by: Olof Johansson <olof@lixom.net>
The dtb targets belong in arch/arm/boot/dts/Makefile now, so move the
newly added davinci targets there.
Signed-off-by: Olof Johansson <olof@lixom.net>
SoC.
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Merge tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci into next/dt
From Sekhar Nori:
These changes add DT boot support to DaVinci DA850
SoC.
* tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da850: generate dtbs for da850 boards
ARM: davinci: add support for am1808 based EnBW CMC board
ARM: davinci: da850 evm: add DT data
ARM: davinci: da850: add SoC DT data
ARM: davinci: da850: add DT boot support
ARM: davinci: da8xx: add DA850 PRUSS support
ARM: davinci: add platform hook to fetch the SRAM pool
ARM: davinci: da850: changed SRAM allocator to shared ram.
ARM: davinci: sram: switch from iotable to ioremapped regions
uio: uio_pruss: replace private SRAM API with genalloc
ARM: davinci: serial: provide API to initialze UART clocks
ARM: davinci: convert platform code to use clk_prepare/clk_unprepare
Signed-off-by: Olof Johansson <olof@lixom.net>
1) Support for PRUSS UIO driver for DA850 SoC
and related SRAM support updates.
2) Prepration for common clock migration
3) Serial support related changes for DA850 DT boot
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Merge tag 'davinci-for-v3.8/soc' of git://gitorious.org/linux-davinci/linux-davinci into next/soc
From Sekhar Nori:
SoC updates for DaVinci. Changes include:
1) Support for PRUSS UIO driver for DA850 SoC
and related SRAM support updates.
2) Prepration for common clock migration
3) Serial support related changes for DA850 DT boot
* tag 'davinci-for-v3.8/soc' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da8xx: add DA850 PRUSS support
ARM: davinci: add platform hook to fetch the SRAM pool
ARM: davinci: da850: changed SRAM allocator to shared ram.
ARM: davinci: sram: switch from iotable to ioremapped regions
uio: uio_pruss: replace private SRAM API with genalloc
ARM: davinci: serial: provide API to initialze UART clocks
ARM: davinci: convert platform code to use clk_prepare/clk_unprepare
Signed-off-by: Olof Johansson <olof@lixom.net>
Since commit 3c7ea4e (mtd: sh_flctl: Add support for error IRQ)
the sh_flctl driver requires the error IRQ line to signal failed
transactions between the flash controller and the NAND chip.
This information is mandatory - else the driver refuses to start
up. We provide it here for the board mackerel.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Modify both AT91 and AVR32 platforms.
Use 7 for it as the sam9260 or the sam9g25 have 7 of them DBGU included.
Reported-by: Joachim Eastwood <joachim.eastwood@jotron.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.
Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.
Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs. It is refined as those CPUs discover what their
actual mapping is.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
In ARM SMP systems the MPIDR register ([23:0] bits) is used to uniquely
identify CPUs.
In order to retrieve the logical CPU index corresponding to a given
MPIDR value and guarantee a consistent translation throughout the kernel,
this patch adds a look-up based on the MPIDR[23:0] so that kernel subsystems
can use it whenever the logical cpu index corresponding to a given MPIDR
value is needed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
As soon as the device tree is unflattened the cpu logical to physical
mapping is carried out in setup_arch to build a proper array of MPIDR and
corresponding logical indexes.
The mapping could have been carried out using the flattened DT blob and
related primitives, but since the mapping is not needed by early boot
code it can safely be executed when the device tree has been uncompressed to
its tree data structure.
This patch adds the arm_dt_init_cpu maps() function call in setup_arch().
If the kernel is not compiled with DT support the function is empty and
no logical mapping takes place through it; the mapping carried out in
smp_setup_processor_id() is left unchanged.
If DT is supported the mapping created in smp_setup_processor_id() is overriden.
The DT mapping also sets the possible cpus mask, hence platform
code need not set it again in the respective smp_init_cpus() functions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
When booting through a device tree, the kernel cpu logical id map can be
initialized using device tree data passed by FW or through an embedded blob.
This patch adds a function that parses device tree "cpu" nodes and
retrieves the corresponding CPUs hardware identifiers (MPIDR).
It sets the possible cpus and the cpu logical map values according to
the number of CPUs defined in the device tree and respective properties.
The device tree HW identifiers are considered valid if all CPU nodes contain
a "reg" property, there are no duplicate "reg" entries and the DT defines a
CPU node whose "reg" property matches the MPIDR[23:0] of the boot CPU.
The primary CPU is assigned cpu logical number 0 to keep the current convention
valid.
Current bindings documentation is included in the patch:
Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
This patch applies some basic changes to the smp_setup_processor_id()
ARM implementation to make the code that builds cpu_logical_map more
uniform across the kernel.
The function now prints the full extent of the boot CPU MPIDR[23:0] and
initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
This patch updates the topology initialization code to use the newly
defined accessors to retrieve the MPIDR affinity levels.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Kernel subsystems other than the topology layer need the MPIDR
mask definitions to access the MPIDR without relying on hardcoded
masks. This patch moves the MPIDR register masks definition to
a header file and defines a macro to simplify access to MPIDR bit fields
representing affinity levels.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Currently, reading /proc/cpuinfo provides userspace with CPU ID of
the CPU carrying out the read from the file. This is fine as long as all
CPUs in the system are the same. With the advent of big.LITTLE and
heterogenous ARM systems this approach provides user space with incorrect
bits of information since CPU ids in the system might differ from the one
provided by the CPU reading the file.
This patch updates the cpuinfo show function so that a read from
/proc/cpuinfo prints HW information for all online CPUs at once, mirroring
x86 behaviour.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
The advent of big.LITTLE ARM platforms requires the kernel to be able
to identify the MIDRs of all online CPUs upon request. MIDRs are stashed
at boot time so that kernel subsystems can detect the MIDR of online CPUs
by simply retrieving per-CPU data updated by all booted CPUs.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reflect architectural support for seccomp filter.
Signed-off-by: Will Drewry <wad@chromium.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On tracehook-friendly platforms, a system call number of -1 falls
through without running much code or taking much action.
ARM is different. This adds a short-circuit check in the trace path to
avoid any additional work, as suggested by Russell King, to make sure
that ARM behaves the same way as other platforms.
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Will Drewry <wad@chromium.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is very little difference in the TIF_SECCOMP and TIF_SYSCALL_WORK
path in entry-common.S, so merge TIF_SECCOMP into TIF_SYSCALL_WORK and
move seccomp into the syscall_trace_enter() handler.
Expanded some of the tracehook logic into the callers to make this code
more readable. Since tracehook needs to do register changing, this portion
is best left in its own function instead of copy/pasting into the callers.
Additionally, the return value for secure_computing() is now checked
and a -1 value will result in the system call being skipped.
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Will Drewry <wad@chromium.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide an ARM implementation of syscall_get_arch. This is a pre-requisite
for CONFIG_HAVE_ARCH_SECCOMP_FILTER.
Signed-off-by: Will Drewry <wad@chromium.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
"Whether" is misspelled in various comments across the tree; this
fixes them. No code changes.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
