Commit Graph

45 Commits

Author SHA1 Message Date
Shawn Lin
34d5ac2af6 PCI: rockchip: Check for pci_scan_root_bus_bridge() failure correctly
pci_scan_root_bus_bridge() returns zero for success, or a negative errno.
A typo in ae13cb9b19 ("PCI: rockchip: Convert PCI scan API to
pci_scan_root_bus_bridge()") treated zero as a failure.

Fix the typo.

Fixes: ae13cb9b19 ("PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2017-07-12 12:50:11 -05:00
Shawn Lin
dc8cca5ef2 PCI: rockchip: Use normal register bank for config accessors
Rockchip's RC has two banks of registers for the root port: a normal bank
that is strictly compatible with the PCIe spec, and a privileged bank that
can be used to change RO bits of root port registers.

When probing the RC driver, we use the privileged bank to do some basic
setup work as some RO bits are hw-inited to wrong value.  But we didn't
change to the normal bank after probing the driver.

This leads to a serious problem when the PME code tries to clear the PME
status by writing PCI_EXP_RTSTA_PME to the register of PCI_EXP_RTSTA.  Per
PCIe 3.0 spec, section 7.8.14, the PME status bit is RW1C.  So the PME code
is doing the right thing to clear the PME status but we find the RC doesn't
clear it but actually setting it to one.  So finally the system trap in
pcie_pme_work_fn() as PCI_EXP_RTSTA_PME is true now forever.  This issue
can be reproduced by booting kernel with pci=nomsi.

Use the normal register bank for the PCI config accessors.  The privileged
bank is used only internally by this driver.

Fixes: e77f847d ("PCI: rockchip: Add Rockchip PCIe controller support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
2017-07-03 08:12:19 -05:00
Shawn Lin
c2741cb6eb PCI: rockchip: Use local struct device pointer consistently
We have a local "struct device *dev" in rockchip_pcie_probe().  Use it
consistently throughout the function.  No functional change intended.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:57 -05:00
Arvind Yadav
94b1d0896a PCI: rockchip: Check for clk_prepare_enable() errors during resume
clk_prepare_enable() can fail here and we must check its return value.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02 18:45:57 -05:00
Shawn Lin
45db3b7029 PCI: rockchip: Configure RC's MPS setting
The default value of MPS for RC is 128 bytes, but actually it could support
256 bytes.  So this patch fixes this issue.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:56 -05:00
Shawn Lin
09cac05097 PCI: rockchip: Reconfigure configuration space header type
Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1
configuration space header should be used when accessing PCIe switch.  So
we need to reconfigure the header according to the bus number we are
accessing.  Otherwise we could not visit the buses behind the switch.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:56 -05:00
Shawn Lin
5667e655e1 PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()
We need to reconfigure the header type later, so split out a new function.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:55 -05:00
Shawn Lin
3166ba040c PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()
Configuration accesses is also part of ATU settings, so let's keep all of
them inside rockchip_pcie_cfg_atu().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:55 -05:00
Shawn Lin
7a1d3b8cb2 PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu()
Rename rockchip_cfg_atu() to keep the name consistent with other functions
in pcie-rockchip.c.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02 18:45:55 -05:00
Shawn Lin
e47ced7783 PCI: rockchip: Control vpcie0v9 for system PM
vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to
work then in S3 if folks assign it DT.  But we should note that there is a
side effect that we could not support beacon wakeup if we disable vpcie0v9
for aggressive power-saving.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
2017-07-02 18:45:54 -05:00
Lorenzo Pieralisi
5a3dc3c1f6 PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ
mapping can be done automatically by PCI core code through the
pci_assign_irq() function instead of resorting to arch-specific
implementation callbacks to carry out the same task which force PCI host
bridge drivers implementation to implement per-arch kludges to carry out a
task that is inherently architecture agnostic.

Add map/swizzle IRQs hooks to the rockchip PCI host driver to move the IRQ
allocation into core code and stop relying on arch-specific callbacks.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wenrui Li <wenrui.li@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02 16:51:19 -05:00
Lorenzo Pieralisi
ae13cb9b19 PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.

Convert PCI rockchip host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wenrui Li <wenrui.li@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02 16:14:26 -05:00
Bjorn Helgaas
0b0ee66c4f Merge branch 'pci/ioremap' into next
* pci/ioremap:
  PCI: versatile: Update PCI config space remap function
  PCI: keystone-dw: Update PCI config space remap function
  PCI: layerscape: Update PCI config space remap function
  PCI: hisi: Update PCI config space remap function
  PCI: tegra: Update PCI config space remap function
  PCI: xgene: Update PCI config space remap function
  PCI: armada8k: Update PCI config space remap function
  PCI: designware: Update PCI config space remap function
  PCI: iproc-platform: Update PCI config space remap function
  PCI: qcom: Update PCI config space remap function
  PCI: rockchip: Update PCI config space remap function
  PCI: spear13xx: Update PCI config space remap function
  PCI: xilinx-nwl: Update PCI config space remap function
  PCI: xilinx: Update PCI config space remap function
  PCI: ECAM: Map config region with pci_remap_cfgspace()
  PCI: Implement devm_pci_remap_cfgspace()
  devres: fix devm_ioremap_*() offset parameter kerneldoc description
  ARM: Implement pci_remap_cfgspace() interface
  ARM64: Implement pci_remap_cfgspace() interface
  linux/io.h: Add pci_remap_cfgspace() interface
  PCI: Remove __weak tag from pci_remap_iospace()
2017-04-28 10:34:05 -05:00
Lorenzo Pieralisi
995b76e48f PCI: rockchip: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wenrui Li <wenrui.li@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-24 13:53:15 -05:00
Brian Norris
b0308c5419 PCI: rockchip: Modularize
Now that we've exported pci_remap_iospace() and added proper remove()
support, there's no reason this can't be a loadable module.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-21 11:01:46 -05:00
Brian Norris
073d3dbe9a PCI: rockchip: Add remove() support
Currently, if we try to unbind the platform device, the remove will
succeed, but the removal won't undo most of the registration, leaving
partially-configured PCI devices in the system.

This allows, for example, a simple 'lspci' to crash the system, as it will
try to touch the freed (via devm_*) driver structures, e.g., on RK3399:

  # echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind
  # lspci

So let's implement device remove().

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-04-21 10:54:35 -05:00
Shawn Lin
64d6ea602c PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port
All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.

Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: jeffy.chen <jeffy.chen@rock-chips.com>
2017-04-11 16:27:02 -05:00
Shawn Lin
55021718b9 PCI: rockchip: Advertise 128-byte Read Completion Boundary support
Rockchip Root Ports support either 64 or 128 byte Read Completion Boundary
(RCB).  Set the RCB bit in the Link Control register to indicate this.

A 128 byte RCB significantly improves performance of NVMe with libaio.

[bhelgaas: changelog]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
2017-04-03 16:04:48 -05:00
Brian Norris
deb518f6ae PCI: rockchip: Make 'return 0' more obvious in probe()
There's no way to get here with 'err != 0'.  Just return 0 to be more
obvious and prevent future changes from accidentally erroring out here
without going through the right error paths.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-23 17:24:34 -05:00
Bjorn Helgaas
73edd2b180 PCI: rockchip: Unindent rockchip_pcie_set_power_limit()
If regulator_get_current_limit() returns 0 or error, return early so the
body of the function doesn't have to be indented as the body of an "if"
statement.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-03-23 17:21:26 -05:00
Brian Norris
5fcaa0051d PCI: rockchip: Handle regulator_get_current_limit() failure correctly
regulator_get_current_limit() can return negative error codes.  We saved
the return value in an unsigned "curr", and a subsequent check interpreted
a negative error code as a positive (invalid) current limit.

Save the return code as a signed value, which avoids messages like this,
seen on Samsung Chromebook Plus:

  rockchip-pcie f8000000.pcie: invalid power supply

[bhelgaas: changelog]
Fixes: 4816c4c7b8 ("PCI: rockchip: Provide captured slot power limit and scale")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-03-23 17:09:12 -05:00
Shawn Lin
5800790a92 PCI: rockchip: Set vendor ID from local core config space
The TRM says the vendor ID in the RC's configure space can be rewritten
and the value must be the same as the value read from the local core
configure space.  But we misread that and didn't notice it before.  Actually
we should only able to rewrite it from the local core configure space.

Fix that issue to make lspci show the correct IP vendor infomation.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-17 14:13:05 -06:00
Shawn Lin
f1d722b607 PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource list
rockchip_pcie_probe() calls of_pci_get_host_bridge_resources() to parse
resources from DT and build a resource list.  The caller is responsible for
disposing of the resource list.  This is normally done by
pci_release_host_bridge_dev() when the host bridge is removed.

If the host bridge probe fails, dispose of the resource list in the probe
error path.

[bhelgaas: changelog]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-10 15:42:01 -06:00
Arnd Bergmann
0b351c986a PCI: rockchip: Mark PM functions as __maybe_unused
When CONFIG_PM_SLEEP is disabled, we get harmless build warnings:

  host/pcie-rockchip.c:1267:12: error: 'rockchip_pcie_resume_noirq' defined but not used [-Werror=unused-function]
  host/pcie-rockchip.c:1240:12: error: 'rockchip_pcie_suspend_noirq' defined but not used [-Werror=unused-function]

Marking both functions as __maybe_unused avoids the warning without the
need for #ifdef around them.

Fixes: 013dd3d5e1 ("PCI: rockchip: Add system PM support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-01-30 14:52:15 -06:00
Shawn Lin
7faebda21d PCI: rockchip: Use readl_poll_timeout() instead of open-coding it
Use readl_poll_timeout() instead of open-coding it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-01-30 14:50:37 -06:00
Shawn Lin
afc9595ea4 PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"
Rockchip's RC produces a 100MHz reference clock but there are two methods
for the PHY to generate it:

  (1) Use the system PLL to generate a 100MHz clock.  The PHY will relock
      it, filter signal noise, and output the reference clock.  ASPM L0s
      works correctly, but circuit noise issues make it difficult to pass
      the TX compatibility test.

  (2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the
      PHY's PLL to generate 100MHz internally.  In this case, exit from
      ASPM L0s sometimes fails due to a design error in the RC receiver
      circuit.  Even if we use extended-synch, the PHY sometimes fails to
      relock the bits from FTS, which will hang the system.

We want the flexibility to use both clocking methods, so add a DT property,
"aspm-no-l0s".  If that's present, disable L0s to avoid the issues with
case (2).

[bhelgaas: changelog]
Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
2017-01-12 15:31:43 -06:00
Shawn Lin
013dd3d5e1 PCI: rockchip: Add system PM support
Add system PM support for Rockchip's RC.  For pre S3, the EP is configured
into D3 state which guarantees the link state should be in L1.  So we could
send PME_Turn_Off message to the EP and wait for its ACK to make the link
state into L2 or L3 without the aux-supply.  This could help save more
power which I think should be very important for mobile devices.

As note that there is a 5s timeout for RC to wait for the PMA_ACK after
sending PME_Turn_Off.  Technically it should depend on the hierarchy of
devices but seems PCIe core framework doesn't handle the L2/3 for S3 at
all.  So that means we should presume to set a default value for PME_ACK.
From the bug report[1], we could find a statement that Microsoft Windows
versions typically wait for 5 seconds.  So we are prone to take 5s for this
timeout here.

[1] https://lists.launchpad.net/kernel-packages/msg123315.html
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2017-01-11 12:22:47 -06:00
Bjorn Helgaas
44b83b32e7 Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip:
  PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
  PCI: rockchip: Split out rockchip_cfg_atu()
  PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS
  PCI: rockchip: Correct the use of FTS mask
  PCI: rockchip: Remove the pointer to L1 substate cap
  PCI: rockchip: Specify the link capability
  PCI: rockchip: Fix negotiated lanes calculation
  PCI: rockchip: Add Kconfig COMPILE_TEST
  PCI: rockchip: Mark RC as common clock architecture
  PCI: rockchip: Provide captured slot power limit and scale
  PCI: rockchip: Add three new resets as required properties
  PCI: Don't attempt to claim shadow copies of ROM
  PCI: designware: Check for iATU unroll support after initializing host
  PCI: qcom: Fix pp->dev usage before assignment
  PCI: designware-plat: Update author email address
  PCI: layerscape: Fix drvdata usage before assignment
  PCI: designware-plat: Change maintainer to Jose Abreu
2016-12-12 11:25:11 -06:00
Shawn Lin
0722bdd296 PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the
logic of reset control and reuse rockchip_pcie_init_port() later which
should fully follow the cold boot procedure of ROM code.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-07 15:08:25 -06:00
Shawn Lin
9e663d3f11 PCI: rockchip: Split out rockchip_cfg_atu()
Split out a new function, rockchip_cfg_atu(), in order to re-configure the
ATU when missing these information after wakeup from S3.

[bhelgaas: add "dev" temporary, return 0 when known]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-07 15:06:20 -06:00
Shawn Lin
f37500b8aa PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS
PCIE_RC_CONFIG_LCS contains control and status bits specific to the PCIe
link.  The layout for this register looks the same as the existing
PCI_EXP_LNKCTL and PCI_EXP_LNKSTA.  So let's reuse them.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:06:00 -06:00
Brian Norris
a45e2611b9 PCI: rockchip: Correct the use of FTS mask
We're trying to mask out bits[23:8] while retaining [32:24, 7:0], but we're
doing the inverse.  That doesn't have too much effect, since we're setting
all the [23:8] bits to 1, and the other bits are only relevant for modes
we're currently not using.  But we should get this right.

Fixes: ca19890840 ("PCI: rockchip: Fix wrong transmitted FTS count")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-12-07 15:06:00 -06:00
Shawn Lin
77bc68cf17 PCI: rockchip: Remove the pointer to L1 substate cap
Per the errata of TRM, the RC can't support L1 substate, so remove the L1
substate cap as well as operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.

Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
f2fb5b8f2a PCI: rockchip: Specify the link capability
rk3399 supports PCIe 2.x link speeds marginally at best, and on some
boards, the link won't train at 5 GT/s at all.  Rather than sacrifice 500ms
waiting for training that will never happen, let's use the helper function,
of_pci_get_max_link_speed(), to get the max link speed from DT and specify
link capability.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
45e9320f3a PCI: rockchip: Fix negotiated lanes calculation
The calculation of negotiated lanes is wrong: it should be shifted by
PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by
PCIE_CORE_PL_CONF_LANE_MASK instead.  Let's fix it.

Fixes: e77f847df5 ("PCI: rockchip: Add Rockchip PCIe controller support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:59 -06:00
Shawn Lin
b8ab8e041c PCI: rockchip: Mark RC as common clock architecture
The default value of common clock configuration is zero indicating
Rockchip's RC is using asynchronous clock architecture but actually we are
using common clock.  This will confuse some EP drivers if they need some
different settings referring to this value.

Set the Common Clock Configuration bit in the Link Control Register.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:58 -06:00
Shawn Lin
4816c4c7b8 PCI: rockchip: Provide captured slot power limit and scale
If vpcie3v3 is available, we could provide these information via RC's
configure register to make EP able to know the power limit.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07 15:05:58 -06:00
Bjorn Helgaas
fb26592301 PCI: Warn on possible RW1C corruption for sub-32 bit config writes
Hardware that supports only 32-bit config writes is not spec-compliant.
For example, if software performs a 16-bit write, we must do a 32-bit read,
merge in the 16 bits we intend to write, followed by a 32-bit write.  If
the 16 bits we *don't* intend to write happen to have any RW1C (write-one-
to-clear) bits set, we just inadvertently cleared something we shouldn't
have.

Add a rate-limited warning when we do sub-32 bit config writes.  Remove
similar probe-time warnings from some of the affected host bridge drivers.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Enthusiastically-Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>	# rockchip
Acked-by: Thierry Reding <treding@nvidia.com>
2016-11-21 16:25:39 -06:00
Shawn Lin
31a3a7b5b2 PCI: rockchip: Add three new resets as required properties
pm_rst, aclk_rst, pclk_rst was controlled by ROM code so the software
wasn't needed to control it again in theory.  But it didn't work properly,
so we do need to do it again and add enough delay between the assert of
pm_rst and the deassert of pm_rst.  The Soc intergrated with this
controller, rk3399, is still under MP test internally, so the backward
compatibility won't be a big deal.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
2016-11-10 11:14:37 -06:00
Dan Carpenter
08015ee0ff PCI: rockchip: Indent "if" statement body
Body of an "if" statement wasn't indented.  Add a tab.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-12 07:14:09 -05:00
Bjorn Helgaas
9d274755c6 PCI: rockchip: Remove unused platform data
The rockchip driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-10-11 23:38:10 -05:00
Shawn Lin
ca19890840 PCI: rockchip: Fix wrong transmitted FTS count
If the expected number of FTS aren't received by RC when exiting from L0s,
the LTSSM will fall into recover state, which means it will need to send TS
for retraining which makes the latency of exiting from L0s a little longer
than expected.  This issue is caused by an incorrect reset value of FTS
count on PLC1 register (offset 0x4).  The expected value for Gen1/2 should
be more than 240 and we may leave a little margin here.  Fix this before
starting Gen1 training which will make TS1 contain the correct FTS count.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-04 12:20:22 -05:00
Shawn Lin
58c6990c5e PCI: rockchip: Improve the deassert sequence of four reset pins
Per TRM, we need to deassert the four reset pins simultaneously.  Currently
the reset framework doesn't support that so we did it one by one.  It seems
no side effect found but it does impact the state machine of controller, so
sometimes the change speed bit is not set when sending training sequence
from recover state.  After the silicon RTL review from SoC guys, we don't
need to do the sequence recommended by TRM, and could just move the
deassert of mgmt_sticky_rst to the first place.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-10-04 12:18:25 -05:00
Rajat Jain
277743ef61 PCI: rockchip: Increase the Max Credit update interval
Increase the likelihood of link state to automatically go to L1 and save
some power.

The default credit update interval of 7.5 us results in the rootport
sending UpdateFC-P and UpdateFC-NP packets too often, thus resulting in the
link never going to L1, and always staying in L0/L0s.  The value 24 us was
chosen after some experiments and peeking over the PCIe bus to see that we
do enter L1 substate when there is not enough traffic on the PCIe bus.

Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-10-04 12:16:03 -05:00
Shawn Lin
e77f847df5 PCI: rockchip: Add Rockchip PCIe controller support
Add support for the Rockchip PCIe controller found on RK3399 SoC platform.

[bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other
fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me,
uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-09-03 11:41:09 -05:00