It was the last platform under gt64120 and will fit better into the new
platform makefile scheme, if moved.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[Ralf: Remove a forgotten -Werror in Pb1200 Makefile.]
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1319/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replace deprecated DMA_32BIT_MASK with DMA_BIT_MASK. This is needed because
the new style platform makefiles will enable -Werror.
cc1: warnings being treated as errors
arch/mips/alchemy/devboards/db1200/platform.c:219: error: 'DMA_nnBIT_MASK' is deprecated
arch/mips/alchemy/devboards/db1200/platform.c:226: error: 'DMA_nnBIT_MASK' is deprecated
arch/mips/alchemy/devboards/db1200/platform.c:388: error: 'DMA_nnBIT_MASK' is deprecated
arch/mips/alchemy/devboards/db1200/platform.c:393: error: 'DMA_nnBIT_MASK' is deprecated
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
To: linux-mips@linux-mips.org
Acked-by: Manuel Lauss <manuel.lauss@googlemail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1427/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Preparatory step for moving Alchemy over to new MIPS Platform
build system support.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/1318/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move platform specific definitions to the platfrom directories.
Each platform shall do the following:
1) include an entry in arch/mips/Kbuild.platforms
2) add relevant definitions to arch/mips/<platform>/Platform
This commits changes ar7 to the new scheme as an example.
Introducing a platform speecific Platfrom file has following advantages:
1) decentralization of platfrom definitions
2) simplification af arch/mips/Makefile
3) force all platfrom to build with -Werror (done in arch/mips/Kbuild)
[Ralf: Remove forgotten -Werror from AR7 Makefile]
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
To: linux-mips <linux-mips@linux-mips.org>
To: Wu Zhangjin <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1302/
Patchwork: http://patchwork.linux-mips.org/patch/1308/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Adding subdirs-ccflags-y := -Werror to arch/mips/Kbuild
let us in one go cover all files with -Werror.
In addition this allows us to remove the
individual -Werror definition in various Makefile.
Adding the definition to Kbuild as a recursive
option help us not to forget to do so.
With this change we now compile arch/mips/kernel/cpufreq with -Werror
One drawback:
When specifying a subdirectory covered by the Kbuild file like this:
make arch/mips/kernel/
then kbuild fails to pick up the -Werror definition.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
To: linux-mips <linux-mips@linux-mips.org>
To: Wu Zhangjin <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1301/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/dec/promcon.c:37: ERROR: that open brace { should be on the previous line
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1270/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pmc-sierra/yosemite/ht-irq.c:38: ERROR: code indent should use tabs where possible
arch/mips/pmc-sierra/yosemite/ht-irq.c:39: ERROR: code indent should use tabs where possible
arch/mips/pmc-sierra/yosemite/ht-irq.c:40: ERROR: code indent should use tabs where possible
arch/mips/pmc-sierra/yosemite/ht-irq.c:43: ERROR: code indent should use tabs where possible
arch/mips/pmc-sierra/yosemite/ht-irq.c:44: ERROR: code indent should use tabs where possible
arch/mips/pmc-sierra/yosemite/ht-irq.c:45: ERROR: code indent should use tabs where possible
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1268/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replace phys_to_dma()/dma_to_phys() looping algorithm with an O(1) algorithm
The approach taken is inspired by the sparse memory implementation: take a
certain number of high-order bits off the address them, use this as an
index into a table containing an offset to the desired address and add
it to the original value. There is a table for mapping physical addresses
to DMA addresses and another one for the reverse mapping. The table sizes
depend on how fine-grained the mappings need to be; Coarser granularity
less to smaller tables. On a processor with 32-bit physical and DMA
addresses, with 4 MIB granularity, memory usage is two 2048-byte arrays.
Each 32-byte cache line thus covers 64 MiB of address space.
Also, renames phys_to_bus() to phys_to_dma() and bus_to_phys() to
dma_to_phys() to align with kernel usage.
[Ralf: Fixed silly build breakage due to stackoverflow warning caused by
huge array on stack.]
Signed-off-by: David VomLehn <dvomlehn@cisco.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1257/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CC arch/mips/alchemy/mtx-1/board_setup.o
{standard input}: Assembler messages:
{standard input}:263: Error: opcode not supported on this processor: mips1 (mips1) `sync'
{standard input}:274: Error: opcode not supported on this processor: mips1 (mips1) `sync'
{standard input}:296: Error: opcode not supported on this processor: mips1 (mips1) `sync'
[...]
Any .set mipsX statement other than .set mips0 at the end of inline
assembler is a big fat bug.
Introduced by 9482eabeca315c0276ffb50026b7482481b7097b (linux-mips.org) rsp.
32fd6901a6 (kernel.org).
While at it, fix the same issue in
arch/mips/alchemy/devboards/pb1000/board_setup.c
arch/mips/alchemy/xxs1500/board_setup.c
as well.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
B43_pci_bridge is needed to use the b43 driver with brcm47xx. Activate it
by default if PCI is available.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1510/
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The previous patch 4a86f2d27733f610e642649aca3e82e86fca9e22 (lmo) rsp.
84a6fcb368 (kernel.org) was wrong.
The BCM47xx architecture maps the ram into a 128MB address space. It
will be spaced there as often as goes into the 128MB. Detection tries to
find the position where the same memory is found. When reading beyond
128MB the processor will throw an exception. If 128MB RAM is installed,
it will not find a memory alias because it tries to read beyond the 128MB
border. Now it just assumes 128MB installed ram if it can not find an
alias.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1508/
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When building with a gcc-4.4.x toolchain that is configured to produce
32-bits executables by default, we will produce __lshrti3 in sched_clock()
which is never resolved so the kernel fails to link. Unconditionally use
the inline assembly version as suggested by David Daney, which works around
the issue.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1514/
Acked-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The 'mult' element of struct clock_event_device must never be wider
than 32-bits. If it were, it would get truncated when used by
clockevent_delta2ns() when this calls do_div().
We can meet this requirement by using clockevent_set_clock() to set
the MULT and SHIFT values.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1253/
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The include is unecessary and will when building the IP35 result in
recursive header inclusion spaghetti.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
With SLAB, it works without ARCH_KMALLOC_MINALIGN, but with SLOB/SLUB,
ARCH_KMALLOC_MINALIGN is required to ensure alignment of kmalloced
buffer.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1248/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* master.kernel.org:/home/rmk/linux-2.6-arm:
cyber2000fb: fix console in truecolor modes
cyber2000fb: fix machine hang on module load
SA1111: Eliminate use after free
ARM: Fix Versatile/Realview/VExpress MMC card detection sense
ARM: 6279/1: highmem: fix SMP preemption bug in kmap_high_l1_vipt
ARM: Add barriers to io{read,write}{8,16,32} accessors as well
ARM: 6273/1: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE
ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
ARM: 6271/1: Introduce *_relaxed() I/O accessors
ARM: 6275/1: ux500: don't use writeb() in uncompress.h
ARM: 6270/1: clean files in arch/arm/boot/compressed/
ARM: Fix csum_partial_copy_from_user()
__sa1111_remove always frees its argument, so the subsequent reference to
sachip->saved_state represents a use after free. __sa1111_remove does not
appear to use the saved_state field, so the patch simply frees it first.
A simplified version of the semantic patch that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression E,E2;
@@
__sa1111_remove(E)
...
(
E = E2
|
* E
)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The MMC card detection sense has become really confused with negations
at various levels, leading to some platforms not detecting inserted
cards. Fix this by converting everything to positive logic throughout,
thereby getting rid of these negations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
smp_processor_id() must not be called from a preemptible context (this
is checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so.
This lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth
could be incremented, causing a BUG_ON(*depth <= 0); in
kunmap_high_l1_vipt().
The solution is to move the call to smp_processor_id() after the call
to preempt_disable().
Originally by: Andrew Howe <ahowe@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Acked-by: Nicolas Pitre <nico.as.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ioread/iowrite accessors also need barriers as they're used in
place of readl/writel et.al. in portable drivers. Create __iormb()
and __iowmb() which are conditionally defined to be barriers dependent
on ARM_DMA_MEM_BUFFERABLE, and always use these macros in the accessors.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When the coherent DMA buffers are mapped as Normal Non-cacheable
(ARM_DMA_MEM_BUFFERABLE enabled), buffer accesses are no longer ordered
with Device memory accesses causing failures in device drivers that do
not use the mandatory memory barriers before starting a DMA transfer.
LKML discussions led to the conclusion that such barriers have to be
added to the I/O accessors:
http://thread.gmane.org/gmane.linux.kernel/683509/focus=686153http://thread.gmane.org/gmane.linux.ide/46414http://thread.gmane.org/gmane.linux.kernel.cross-arch/5250
This patch introduces a wmb() barrier to the write*() I/O accessors to
handle the situations where Normal Non-cacheable writes are still in the
processor (or L2 cache controller) write buffer before a DMA transfer
command is issued. For the read*() accessors, a rmb() is introduced
after the I/O to avoid speculative loads where the driver polls for a
DMA transfer ready bit.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
