Add MCT device tree node for Exynos4210, Exynos4212, Exynos4412
and Exynos5250.
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Fix the incorrect compatible property value of pinctrl for EXYNOS4 SoCs.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree nodes for power domains available
on EXYNOS4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds necessary source definations needed for TMU driver and
adds devicetree node for exynos4210.
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch reworks wake-up interrupt handling in pinctrl-exynos driver,
so each pin bank, which provides wake-up interrupts, has its own IRQ
domain.
Information about whether given pin bank provides wake-up interrupts,
how many and whether they are separate or muxed are parsed from device
tree.
It gives following advantages:
- interrupts can be specified in device tree in a more readable way,
e.g. :
device {
/* ... */
interrupt-parent = <&gpx2>;
interrupts = <4 0>;
/* ... */
};
- the amount and layout of interrupts is not hardcoded in the code
anymore, but defined in SoC-specific structure
- bank and pin of each wake-up interrupt can be easily identified, to
allow operations, such as setting the pin to EINT function, from
irq_set_type() callback
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of registering one IRQ domain for all pin banks of a pin
controller, this patch implements registration of per-bank domains.
At a cost of a little memory overhead (~2.5KiB for all GPIO interrupts
of Exynos4x12) it simplifies driver code and device tree sources,
because GPIO interrupts can be now specified per banks.
Example:
device {
/* ... */
interrupt-parent = <&gpa1>;
interrupts = <3 0>;
/* ... */
};
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch is a preparation for converting the pinctrl-samsung driver to
one GPIO chip and IRQ domain per bank. It allows particular banks to be
specified using their phandles.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most definitions from exynos4210.dtsi can be applied for other SoCs from
EXYNOS4 line as well, so move the common part into separate file that
can be included by dtsi files of other EXYNOS4 SoCs (as well as current
exynos4210.dtsi).
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: Dongjin Kim <dongjin.kim@agreeyamobility.net>
submitted a similar patch 'Add DTS files derived from common EXYNOS4'
before this but I picked this up because of included exynos4x12 stuff]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add pinctrl driver nodes for the three instances of pin controllers
in SAMSUNG EXYNOS4210 SoC and add the pin group nodes available in the
each of those three instances.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Bindings for DMA channels are still under discussion and will
change once this has been resolved. Therefore we mark them
the newly added ones as preliminary. Let's hope nobody starts
relying on them...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device nodes for the three instances of spi controllers in
EXYNOS4 platforms. Enable instance SPI 2 for SMDKV310 board and
disable all spi instances for Origen board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add node for EXYNOS4 interrupt combiner controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit db0d4db22a ('ARM: gic: allow GIC to support non-banked setups)
requires a cpu-offset property to be specified for non-banked gic
controllers, which is the case for Exynos4.
Reported-and-Tested-by: Karol Lewandowski <k.lewandowsk@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add initial dts file for EXYNOS4210 SoC. This dts file describes
the SoC specific devices and properties. Along with this, add dts
file for Samsung's SMDKV310 board and Insignal's ORIGEN board which
uses the EXYNOS4210 dts file and extends it to describe the board
specific properties.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
