Alex Deucher
|
f6c3947893
|
drm/amdgpu: add the VCE 4.0 register headers
These are the Video Compression Engine registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:28 -04:00 |
|
Alex Deucher
|
7008d577d6
|
drm/amdgpu: add the UVD 7.0 register headers
These are the Unifed Video Decoder registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:28 -04:00 |
|
Alex Deucher
|
893f25540e
|
drm/amdgpu: add THM 9.0 register headers
These are the THerMal control registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:27 -04:00 |
|
Alex Deucher
|
63d311d9b4
|
drm/amdgpu: add SMUIO 9.0 register headers
These are the System Managment Unit IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:26 -04:00 |
|
Alex Deucher
|
456f97704f
|
drm/amdgpu: add SDMA 4.0 register headers
These are the System DMA register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:26 -04:00 |
|
Alex Deucher
|
5a8288c0f9
|
drm/amdgpu: add OSSSYS 4.0 register headers
These are the OS Services register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:25 -04:00 |
|
Alex Deucher
|
198b746016
|
drm/amdgpu: add NBIO 6.1 register headers
These are the Bus IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:24 -04:00 |
|
Alex Deucher
|
61e04478b2
|
drm/amdgpu: add NBIF 6.1 register headers
These are the Bus InterFace registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:23 -04:00 |
|
Alex Deucher
|
3ec127a075
|
drm/amdgpu: add MP 9.0 register headers
MP is the system management controller on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:23 -04:00 |
|
Alex Deucher
|
68c7d13052
|
drm/amdgpu: add the MMHUB 1.0 register headers
Add the MultiMedia Hub registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:22 -04:00 |
|
Alex Deucher
|
bcfb47cdd7
|
drm/amdgpu: add the HDP 4.0 register headers
These are the Host Data Path registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:21 -04:00 |
|
Alex Deucher
|
5585476e44
|
drm/amdgpu: add the GC 9.0 register headers
Add the Graphics Core register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:21 -04:00 |
|
Alex Deucher
|
4adc5ab813
|
drm/amdgpu: Add the DCE 12.0 register headers
These are the register headers for the Display
and Composition Engine on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:20 -04:00 |
|
Alex Deucher
|
7fee1fd93b
|
drm/amdgpu: Add ATHUB 1.0 register headers
ATHUB is part of the memory controller on soc15 asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:19 -04:00 |
|
Alex Deucher
|
733acf561e
|
drm/amdgpu: add vega10_enum.h
This adds the register bitfield enums for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:19 -04:00 |
|
Alex Deucher
|
1fd1cc5640
|
drm/amdgpu: add soc15ip.h
This header defines the IP layout for soc15 based SoCs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
2017-03-29 23:54:18 -04:00 |
|